diff options
| author | Tom Rini <[email protected]> | 2024-06-18 10:29:35 -0600 |
|---|---|---|
| committer | Tom Rini <[email protected]> | 2024-06-18 10:29:35 -0600 |
| commit | ca4becc149e1a0063cc72a7bf071062d415bcaf6 (patch) | |
| tree | 1c2d6759555afc524d5f1234c1c5bbcdd7491585 /board | |
| parent | f8eb6b4a03ff69e8e5919a23fd6287de1155142f (diff) | |
| parent | 680fcbcf55064c5cdf3ef653209da0e925adade6 (diff) | |
Merge patch series "*** Various fixes & improvements for phycore-AM6* SoMs ***"
Wadim Egorov <[email protected]> says:
It includes various fixes and improvements for phyCORE-AM62x and
phyCORE-AM64x SoMs. Notable is the last patch which prepares for use
with future ECC memory fixups.
Diffstat (limited to 'board')
| -rw-r--r-- | board/phytec/common/k3/board.c | 10 | ||||
| -rw-r--r-- | board/phytec/phycore_am62x/phycore-am62x.c | 31 | ||||
| -rw-r--r-- | board/phytec/phycore_am62x/phycore_am62x.env | 2 |
3 files changed, 42 insertions, 1 deletions
diff --git a/board/phytec/common/k3/board.c b/board/phytec/common/k3/board.c index f21e154d4fe..3d7e090ccaa 100644 --- a/board/phytec/common/k3/board.c +++ b/board/phytec/common/k3/board.c @@ -5,6 +5,7 @@ */ #include <env_internal.h> +#include <fdt_support.h> #include <spl.h> #include <asm/arch/hardware.h> @@ -94,3 +95,12 @@ int board_late_init(void) return 0; } #endif + +#if IS_ENABLED(CONFIG_OF_LIBFDT) && IS_ENABLED(CONFIG_OF_BOARD_SETUP) +int ft_board_setup(void *blob, struct bd_info *bd) +{ + fdt_copy_fixed_partitions(blob); + + return 0; +} +#endif diff --git a/board/phytec/phycore_am62x/phycore-am62x.c b/board/phytec/phycore_am62x/phycore-am62x.c index 4a76f1343d7..9f6bc736cbb 100644 --- a/board/phytec/phycore_am62x/phycore-am62x.c +++ b/board/phytec/phycore_am62x/phycore-am62x.c @@ -4,6 +4,7 @@ * Author: Wadim Egorov <[email protected]> */ +#include <asm/arch/hardware.h> #include <asm/io.h> #include <spl.h> #include <fdt_support.h> @@ -46,7 +47,12 @@ static u8 phytec_get_am62_ddr_size_default(void) int dram_init(void) { - u8 ram_size = phytec_get_am62_ddr_size_default(); + u8 ram_size; + + if (!IS_ENABLED(CONFIG_CPU_V7R)) + return fdtdec_setup_mem_size_base(); + + ram_size = phytec_get_am62_ddr_size_default(); /* * HACK: ddrss driver support 2GB RAM by default @@ -91,6 +97,9 @@ int dram_init_banksize(void) { u8 ram_size; + if (!IS_ENABLED(CONFIG_CPU_V7R)) + return fdtdec_setup_memory_banksize(); + ram_size = phytec_get_am62_ddr_size_default(); switch (ram_size) { case EEPROM_RAM_SIZE_1GB: @@ -173,6 +182,26 @@ int do_board_detect(void) } #endif +#if IS_ENABLED(CONFIG_SPL_BUILD) +void spl_perform_fixups(struct spl_image_info *spl_image) +{ + u64 start[CONFIG_NR_DRAM_BANKS]; + u64 size[CONFIG_NR_DRAM_BANKS]; + int bank; + int ret; + + dram_init(); + dram_init_banksize(); + + for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) { + start[bank] = gd->bd->bi_dram[bank].start; + size[bank] = gd->bd->bi_dram[bank].size; + } + + ret = fdt_fixup_memory_banks(spl_image->fdt_addr, start, size, CONFIG_NR_DRAM_BANKS); +} +#endif + #define CTRLMMR_USB0_PHY_CTRL 0x43004008 #define CTRLMMR_USB1_PHY_CTRL 0x43004018 #define CORE_VOLTAGE 0x80000000 diff --git a/board/phytec/phycore_am62x/phycore_am62x.env b/board/phytec/phycore_am62x/phycore_am62x.env index ada3a9233be..42db26a5990 100644 --- a/board/phytec/phycore_am62x/phycore_am62x.env +++ b/board/phytec/phycore_am62x/phycore_am62x.env @@ -1,3 +1,5 @@ +#include <env/ti/k3_dfu.env> + fdtaddr=0x88000000 loadaddr=0x82000000 scriptaddr=0x80000000 |