diff options
| author | Oleksandr Suvorov <[email protected]> | 2022-07-22 17:16:04 +0300 |
|---|---|---|
| committer | Michal Simek <[email protected]> | 2022-07-26 09:34:21 +0200 |
| commit | d7fcbfc19b4e83930a90c834046d4bf7dc3adefe (patch) | |
| tree | aeee634633d84e0bc399e70640807043edf4686e /board | |
| parent | f18adf106576f298ead743a02800c6fdc90d884c (diff) | |
fpga: xilinx: add bitstream flags to driver desc
Store a set of supported bitstream types in xilinx_desc structure.
It will be used to determine whether an FPGA image is able to be
loaded with a given driver.
Signed-off-by: Oleksandr Suvorov <[email protected]>
Tested-by: Ricardo Salveti <[email protected]>
Tested-by: Adrian Fiergolski <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Michal Simek <[email protected]>
Diffstat (limited to 'board')
| -rw-r--r-- | board/xilinx/versal/board.c | 5 | ||||
| -rw-r--r-- | board/xilinx/zynqmp/zynqmp.c | 5 |
2 files changed, 8 insertions, 2 deletions
diff --git a/board/xilinx/versal/board.c b/board/xilinx/versal/board.c index 81663e0cd0e..d8f39be56c8 100644 --- a/board/xilinx/versal/board.c +++ b/board/xilinx/versal/board.c @@ -27,7 +27,10 @@ DECLARE_GLOBAL_DATA_PTR; #if defined(CONFIG_FPGA_VERSALPL) -static xilinx_desc versalpl = XILINX_VERSAL_DESC; +static xilinx_desc versalpl = { + xilinx_versal, csu_dma, 1, &versal_op, 0, &versal_op, NULL, + FPGA_LEGACY +}; #endif int board_init(void) diff --git a/board/xilinx/zynqmp/zynqmp.c b/board/xilinx/zynqmp/zynqmp.c index f7c6e3ed4e3..57259b60a02 100644 --- a/board/xilinx/zynqmp/zynqmp.c +++ b/board/xilinx/zynqmp/zynqmp.c @@ -48,7 +48,10 @@ DECLARE_GLOBAL_DATA_PTR; #if CONFIG_IS_ENABLED(FPGA) && defined(CONFIG_FPGA_ZYNQMPPL) -static xilinx_desc zynqmppl = XILINX_ZYNQMP_DESC; +static xilinx_desc zynqmppl = { + xilinx_zynqmp, csu_dma, 1, &zynqmp_op, 0, &zynqmp_op, NULL, + ZYNQMP_FPGA_FLAGS +}; #endif int __maybe_unused psu_uboot_init(void) |