Merge patch series "arm: omap: Add back omap4 support"

Bastien Curutchet <[email protected]> says:

This series aims to add back the omap4 support. This support was removed
by commit b0ee3fe642c ("arm: ti: Remove omap4 platform support") because
at that moment, none of the OMAP4-based boards had done the migration to
DM_I2C.
My use case is an old product based on the Variscite's omap4 system on
module. I needed to upgrade U-Boot on it for security reasons. I think
that this work could benefit to other people who may have same kind of
product to maintain.

Patch 1 to 3 remove the omap's clock driver dependency to the AM33xx
as it is also present in omap4 platforms. I tested these changes on the
beaglebone black to ensure I didn't break the AM33xx case.

Patch 4 & 5 revert the deletion of the omap4 support. The revert makes
checkpatch.pl angry. I fixed quite a lots of warnings already but it
remains two kinds of warnings:
- CamelCase on timings structure, I left the CamelCase because IMHO it's
  more readable this way.
- #ifdef CONFIG_XYZ shouldn't be used anymore. I left one of this because
  I didn't find a clean way to get rid of it.

Patch 6 adds support for the Variscite's system on module. This system on
module is supported by the Linux project through
ti/omap/omap4-var-som-om44.dtsi

Link: https://lore.kernel.org/r/[email protected]

5 files changed, 226 insertions, 0 deletions

diff --git a/board/variscite/omap4_var_som/Kconfig b/board/variscite/omap4_var_som/Kconfig
new file mode 100644
index 00000000000..dc943b3366e
--- /dev/null
+++ b/board/variscite/omap4_var_som/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_OMAP4_VAR_SOM
+
+config SYS_BOARD
+	default "omap4_var_som"
+
+config SYS_VENDOR
+	default "variscite"
+
+config SYS_CONFIG_NAME
+	default "ti_omap4_common"
+
+endif
diff --git a/board/variscite/omap4_var_som/MAINTAINERS b/board/variscite/omap4_var_som/MAINTAINERS
new file mode 100644
index 00000000000..a8680bc75d3
--- /dev/null
+++ b/board/variscite/omap4_var_som/MAINTAINERS
@@ -0,0 +1,4 @@
+ARM OMAP4 VARISCITE VAR-SOM-OM44 MODULE
+M:	Bastien Curutchet <[email protected]>
+S:	Maintained
+N:	omap4_var_som
diff --git a/board/variscite/omap4_var_som/Makefile b/board/variscite/omap4_var_som/Makefile
new file mode 100644
index 00000000000..c88ab3cac7b
--- /dev/null
+++ b/board/variscite/omap4_var_som/Makefile
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2000, 2001, 2002
+# Wolfgang Denk, DENX Software Engineering, [email protected].
+
+obj-y	:= omap4_var_som.o
diff --git a/board/variscite/omap4_var_som/omap4_var_som.c b/board/variscite/omap4_var_som/omap4_var_som.c
new file mode 100644
index 00000000000..f2fc790dd4b
--- /dev/null
+++ b/board/variscite/omap4_var_som/omap4_var_som.c
@@ -0,0 +1,172 @@
+// SPDX-License-Identifier: GPL-2.0+
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/mmc_host_def.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/gpio.h>
+#include <asm/emif.h>
+#include <asm/global_data.h>
+#include <asm/mach-types.h>
+#include <asm-generic/gpio.h>
+#include <env.h>
+#include <init.h>
+#include <linux/delay.h>
+#include <log.h>
+#include <serial.h>
+
+#include "omap4_var_som_mux.h"
+
+#define VAR_SOM_REV_GPIO		   52
+
+DECLARE_GLOBAL_DATA_PTR;
+
+const struct omap_sysinfo sysinfo = {
+	"Board: OMAP4 VAR-SOM-OM44\n"
+};
+
+struct omap4_scrm_regs *const scrm = (struct omap4_scrm_regs *)0x4a30a000;
+
+/**
+ * @brief board_init
+ *
+ * Return: 0
+ */
+int board_init(void)
+{
+	gpmc_init();
+
+	gd->bd->bi_arch_number = MACH_TYPE_OMAP4_VAR_SOM;
+	gd->bd->bi_boot_params = (0x80000000 + 0x100); /* boot param addr */
+
+	return 0;
+}
+
+static const struct emif_regs emif_regs_hynix_kdpm_400_mhz_1cs = {
+	.sdram_config_init		= 0x80000eb2,
+	.sdram_config			= 0x80001ab2,
+	.ref_ctrl			= 0x000005cd,
+	.sdram_tim1			= 0x10cb0622,
+	.sdram_tim2			= 0x20350d52,
+	.sdram_tim3			= 0x00b1431f,
+	.read_idle_ctrl			= 0x000501ff,
+	.zq_config			= 0x500b3214,
+	.temp_alert_config		= 0x58016893,
+	.emif_ddr_phy_ctlr_1_init	= 0x049ffff5,
+	.emif_ddr_phy_ctlr_1		= 0x049ff418
+};
+
+const struct emif_regs emif_regs_hynix_kdpm_400_mhz_2cs = {
+	.sdram_config_init		= 0x80000eb9,
+	.sdram_config			= 0x80001ab9,
+	.ref_ctrl			= 0x00000618,
+	.sdram_tim1			= 0x10eb0662,
+	.sdram_tim2			= 0x20370dd2,
+	.sdram_tim3			= 0x00b1c33f,
+	.read_idle_ctrl			= 0x000501ff,
+	.zq_config			= 0xd00b3214,
+	.temp_alert_config		= 0xd8016893,
+	.emif_ddr_phy_ctlr_1_init	= 0x049ffff5,
+	.emif_ddr_phy_ctlr_1		= 0x049ff418
+};
+
+/*
+ * emif_get_reg_dump() - emif_get_reg_dump strong function
+ *
+ * @emif_nr - emif base
+ * @regs - reg dump of timing values
+ *
+ * Strong function to override emif_get_reg_dump weak function in sdram_elpida.c
+ */
+void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs)
+{
+	u32 rev;
+
+	gpio_direction_input(VAR_SOM_REV_GPIO);
+	rev = gpio_get_value(VAR_SOM_REV_GPIO);
+
+	if (rev == 1)
+		*regs = &emif_regs_hynix_kdpm_400_mhz_1cs;
+	else
+		*regs = &emif_regs_hynix_kdpm_400_mhz_2cs;
+}
+
+void emif_get_dmm_regs(const struct dmm_lisa_map_regs
+						**dmm_lisa_regs)
+{
+	u32 omap_rev = omap_revision();
+
+	if (omap_rev == OMAP4430_ES1_0)
+		*dmm_lisa_regs = &lisa_map_2G_x_1_x_2;
+	else if (omap_rev == OMAP4430_ES2_3)
+		*dmm_lisa_regs = &lisa_map_2G_x_2_x_2;
+	else if (omap_rev < OMAP4460_ES1_0)
+		*dmm_lisa_regs = &lisa_map_2G_x_2_x_2;
+	else
+		*dmm_lisa_regs = &ma_lisa_map_2G_x_2_x_2;
+}
+
+void emif_get_device_timings(u32 emif_nr,
+			     const struct lpddr2_device_timings **cs0_device_timings,
+			     const struct lpddr2_device_timings **cs1_device_timings)
+{
+	/* Identical devices on EMIF1 & EMIF2 */
+	*cs0_device_timings = &elpida_2G_S4_timings;
+	*cs1_device_timings = NULL;
+}
+
+/**
+ * @brief misc_init_r() - VAR-SOM configuration
+ *
+ * Configure VAR-SOM board specific configurations such as power configurations.
+ *
+ * Return: 0
+ */
+int misc_init_r(void)
+{
+	u32 auxclk, altclksrc;
+
+	auxclk = readl(&scrm->auxclk3);
+	/* Select sys_clk */
+	auxclk &= ~AUXCLK_SRCSELECT_MASK;
+	auxclk |=  AUXCLK_SRCSELECT_SYS_CLK << AUXCLK_SRCSELECT_SHIFT;
+	/* Set the divisor to 2 */
+	auxclk &= ~AUXCLK_CLKDIV_MASK;
+	auxclk |= AUXCLK_CLKDIV_2 << AUXCLK_CLKDIV_SHIFT;
+	/* Request auxilary clock #3 */
+	auxclk |= AUXCLK_ENABLE_MASK;
+
+	writel(auxclk, &scrm->auxclk3);
+
+	altclksrc = readl(&scrm->altclksrc);
+
+	/* Activate alternate system clock supplier */
+	altclksrc &= ~ALTCLKSRC_MODE_MASK;
+	altclksrc |= ALTCLKSRC_MODE_ACTIVE;
+
+	/* enable clocks */
+	altclksrc |= ALTCLKSRC_ENABLE_INT_MASK | ALTCLKSRC_ENABLE_EXT_MASK;
+
+	writel(altclksrc, &scrm->altclksrc);
+
+	return 0;
+}
+
+void set_muxconf_regs(void)
+{
+	if (IS_ENABLED(CONFIG_SPL_BUILD)) {
+		do_set_mux((*ctrl)->control_padconf_core_base,
+			   core_padconf_array_essential,
+			   sizeof(core_padconf_array_essential) /
+			   sizeof(struct pad_conf_entry));
+
+		do_set_mux((*ctrl)->control_padconf_wkup_base,
+			   wkup_padconf_array_essential,
+			   sizeof(wkup_padconf_array_essential) /
+			   sizeof(struct pad_conf_entry));
+	}
+}
+
+int board_mmc_init(struct bd_info *bis)
+{
+	if (IS_ENABLED(CONFIG_MMC))
+		return omap_mmc_init(0, 0, 0, -1, -1);
+}
diff --git a/board/variscite/omap4_var_som/omap4_var_som_mux.h b/board/variscite/omap4_var_som/omap4_var_som_mux.h
new file mode 100644
index 00000000000..fe0b99daf75
--- /dev/null
+++ b/board/variscite/omap4_var_som/omap4_var_som_mux.h
@@ -0,0 +1,32 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+#ifndef _VAR_SOM_OM44_MUX_DATA_H_
+#define _VAR_SOM_OM44_MUX_DATA_H_
+
+#include <asm/arch/mux_omap4.h>
+
+const struct pad_conf_entry core_padconf_array_essential[] = {
+{GPMC_AD0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},  /* sdmmc2_dat0 */
+{GPMC_AD1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},  /* sdmmc2_dat1 */
+{GPMC_AD2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},  /* sdmmc2_dat2 */
+{GPMC_AD3, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},  /* sdmmc2_dat3 */
+{GPMC_NCS2, (PTD | IEN | M3)},  /* gpio52 som rev */
+{GPMC_NOE, (PTU | IEN | OFF_EN | OFF_OUT_PTD | M1)},  /* sdmmc2_clk */
+{GPMC_NWE, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},  /* sdmmc2_cmd */
+{I2C1_SCL, (PTU | IEN | M0)},  /* i2c1_scl */
+{I2C1_SDA, (PTU | IEN | M0)},  /* i2c1_sda */
+{UART3_RX_IRRX, (IEN | M0)},  /* uart3_rx */
+{UART3_TX_IRTX, (M0)},  /* uart3_tx */
+};
+
+const struct pad_conf_entry wkup_padconf_array_essential[] = {
+{PAD0_FREF_CLK3_OUT, (M0)}, /* fref_clk3_out */
+{PAD0_FREF_SLICER_IN, (M0)},  /* fref_slicer_in */
+{PAD1_FREF_CLK_IOREQ, (M0)},  /* fref_clk_ioreq */
+{PAD0_FREF_CLK0_OUT, (M2)},  /* sys_drm_msecure */
+{PAD1_SYS_32K, (IEN | M0)},  /* sys_32k */
+{PAD0_SYS_NRESPWRON, (M0)},  /* sys_nrespwron */
+{PAD1_SYS_NRESWARM, (M0)},  /* sys_nreswarm */
+{PAD0_SYS_PWR_REQ, (PTU | M0)},  /* sys_pwr_req */
+};
+
+#endif /* _VAR_SOM_OM44_MUX_DATA_H_ */