Merge tag 'v2025.10-rc3' into next

Prepare v2025.10-rc3

13 files changed, 334 insertions, 73 deletions

diff --git a/board/andestech/voyager/Kconfig b/board/andestech/voyager/Kconfig
new file mode 100644
index 00000000000..b2e212c3fee
--- /dev/null
+++ b/board/andestech/voyager/Kconfig
@@ -0,0 +1,44 @@
+if TARGET_ANDES_VOYAGER
+
+config SYS_CPU
+	default "andes"
+
+config SYS_BOARD
+	default "voyager"
+
+config SYS_VENDOR
+	default "andestech"
+
+config SYS_SOC
+	default "qilai"
+
+config SYS_CONFIG_NAME
+	default "voyager"
+
+config ENV_SIZE
+	default 0x2000 if ENV_IS_IN_SPI_FLASH
+
+config ENV_OFFSET
+	default 0x1F0000 if ENV_IS_IN_SPI_FLASH
+
+config SPL_TEXT_BASE
+	default 0x400800000
+
+config SPL_OPENSBI_LOAD_ADDR
+	default 0x400000000
+
+config SYS_FDT_BASE
+	hex
+	default 0x81E0000 if OF_SEPARATE
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+	def_bool y
+	select RISCV_ANDES
+	select SUPPORT_SPL
+	select BINMAN if SPL
+	imply SMP
+	imply SPL_RAM_SUPPORT
+	imply SPL_RAM_DEVICE
+	imply OF_HAS_PRIOR_STAGE
+
+endif
diff --git a/board/andestech/voyager/MAINTAINERS b/board/andestech/voyager/MAINTAINERS
new file mode 100644
index 00000000000..b87026ee383
--- /dev/null
+++ b/board/andestech/voyager/MAINTAINERS
@@ -0,0 +1,8 @@
+Andestech Voyager BOARD
+M:	Randolph <[email protected]>
+S:	Maintained
+F:	board/andestech/voyager/
+F:	configs/voyager_spl_defconfig
+F:	doc/board/andestech/voyager.rst
+F:	include/configs/qilai.h
+
diff --git a/board/andestech/voyager/Makefile b/board/andestech/voyager/Makefile
new file mode 100644
index 00000000000..d293e3e2d89
--- /dev/null
+++ b/board/andestech/voyager/Makefile
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2025 Andes Technology Corporation.
+# Randolph Lin, Andes Technology Corporation <[email protected]>
+
+obj-y	:= voyager.o
diff --git a/board/andestech/voyager/voyager.c b/board/andestech/voyager/voyager.c
new file mode 100644
index 00000000000..dc8f1347775
--- /dev/null
+++ b/board/andestech/voyager/voyager.c
@@ -0,0 +1,70 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2025 Andes Technology Corporation
+ * Randolph Lin, Andes Technology Corporation <[email protected]>
+ */
+
+#include <asm/csr.h>
+#include <asm/global_data.h>
+#include <asm/sbi.h>
+#include <config.h>
+#include <cpu_func.h>
+#include <dm.h>
+#include <env.h>
+#include <fdtdec.h>
+#include <flash.h>
+#include <image.h>
+#include <init.h>
+#include <linux/io.h>
+#include <net.h>
+#include <spl.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int dram_init(void)
+{
+	return fdtdec_setup_mem_size_base();
+}
+
+int dram_init_banksize(void)
+{
+	return fdtdec_setup_memory_banksize();
+}
+
+#ifdef CONFIG_SPL_BOARD_INIT
+void spl_board_init(void)
+{
+	/* enable andes-l2 cache */
+	if (!CONFIG_IS_ENABLED(SYS_DCACHE_OFF))
+		enable_caches();
+}
+#endif
+
+#ifdef CONFIG_BOARD_EARLY_INIT_R
+int board_early_init_r(void)
+{
+	/* enable andes-l2 cache */
+	if (!CONFIG_IS_ENABLED(SYS_DCACHE_OFF))
+		enable_caches();
+
+	return 0;
+}
+#endif
+
+#ifdef CONFIG_SPL
+void board_boot_order(u32 *spl_boot_list)
+{
+	u8 i;
+	u32 boot_devices[] = {
+#ifdef CONFIG_SPL_RAM_SUPPORT
+		BOOT_DEVICE_RAM,
+#endif
+#ifdef CONFIG_SPL_MMC
+		BOOT_DEVICE_MMC1,
+#endif
+	};
+
+	for (i = 0; i < ARRAY_SIZE(boot_devices); i++)
+		spl_boot_list[i] = boot_devices[i];
+}
+#endif
diff --git a/board/microchip/mpfs_icicle/Kconfig b/board/microchip/mpfs_icicle/Kconfig
index 6e8c479e955..760dffc488b 100644
--- a/board/microchip/mpfs_icicle/Kconfig
+++ b/board/microchip/mpfs_icicle/Kconfig
@@ -59,5 +59,9 @@ config BOARD_SPECIFIC_OPTIONS # dummy
 	imply MTD_SPI_NAND
 	imply CMD_MTD
 	imply CMD_MTDPARTS
+	imply DM_MAILBOX
+	imply MPFS_MBOX
+	imply MISC
+	imply MPFS_SYSCONTROLLER
 
 endif
diff --git a/board/microchip/mpfs_icicle/mpfs_icicle.c b/board/microchip/mpfs_icicle/mpfs_icicle.c
index ba622e38ee5..739a9b6cd76 100644
--- a/board/microchip/mpfs_icicle/mpfs_icicle.c
+++ b/board/microchip/mpfs_icicle/mpfs_icicle.c
@@ -4,52 +4,21 @@
  * Padmarao Begari <[email protected]>
  */
 
-#include <dm.h>
-#include <env.h>
-#include <init.h>
 #include <asm/global_data.h>
 #include <asm/io.h>
 #include <asm/sections.h>
+#include <dm.h>
+#include <dm/devres.h>
+#include <env.h>
+#include <linux/compat.h>
+#include <mpfs-mailbox.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
-#define MPFS_SYSREG_SOFT_RESET		((unsigned int *)0x20002088)
-#define MPFS_SYS_SERVICE_CR		((unsigned int *)0x37020050)
-#define MPFS_SYS_SERVICE_SR		((unsigned int *)0x37020054)
-#define MPFS_SYS_SERVICE_MAILBOX	((unsigned char *)0x37020800)
-
+#define MPFS_SYSREG_SOFT_RESET	((unsigned int *)0x20002088)
 #define PERIPH_RESET_VALUE		0x1e8u
-#define SERVICE_CR_REQ			0x1u
-#define SERVICE_SR_BUSY			0x2u
 
-static void read_device_serial_number(u8 *response, u8 response_size)
-{
-	u8 idx;
-	u8 *response_buf;
-	unsigned int val;
-
-	response_buf = (u8 *)response;
-
-	writel(SERVICE_CR_REQ, MPFS_SYS_SERVICE_CR);
-	/*
-	 * REQ bit will remain set till the system controller starts
-	 * processing.
-	 */
-	do {
-		val = readl(MPFS_SYS_SERVICE_CR);
-	} while (SERVICE_CR_REQ == (val & SERVICE_CR_REQ));
-
-	/*
-	 * Once system controller starts processing the busy bit will
-	 * go high and service is completed when busy bit is gone low
-	 */
-	do {
-		val = readl(MPFS_SYS_SERVICE_SR);
-	} while (SERVICE_SR_BUSY == (val & SERVICE_SR_BUSY));
-
-	for (idx = 0; idx < response_size; idx++)
-		response_buf[idx] = readb(MPFS_SYS_SERVICE_MAILBOX + idx);
-}
+static unsigned char mac_addr[6];
 
 #if defined(CONFIG_MULTI_DTB_FIT)
 int board_fit_config_name_match(const char *name)
@@ -145,13 +114,35 @@ int board_late_init(void)
 {
 	u32 ret;
 	int node;
-	u8 idx;
-	u8 device_serial_number[16] = { 0 };
-	unsigned char mac_addr[6];
-	char icicle_mac_addr[20];
+	u8 device_serial_number[16] = {0};
 	void *blob = (void *)gd->fdt_blob;
+	struct udevice *dev;
+	struct mpfs_sys_serv *sys_serv_priv;
+
+	ret = uclass_get_device_by_name(UCLASS_MISC, "syscontroller", &dev);
+	if (ret) {
+		debug("%s: system controller setup failed\n", __func__);
+		return ret;
+	}
+
+	sys_serv_priv = kzalloc(sizeof(*sys_serv_priv), GFP_KERNEL);
+	if (!sys_serv_priv)
+		return -ENOMEM;
 
-	read_device_serial_number(device_serial_number, 16);
+	sys_serv_priv->dev = dev;
+
+	sys_serv_priv->sys_controller = mpfs_syscontroller_get(dev);
+	ret = IS_ERR(sys_serv_priv->sys_controller);
+	if (ret) {
+		debug("%s:  Failed to register system controller sub device ret=%d\n", __func__, ret);
+		return -ENODEV;
+	}
+
+	ret = mpfs_syscontroller_read_sernum(sys_serv_priv, device_serial_number);
+	if (ret) {
+		printf("Cannot read device serial number\n");
+		return -EINVAL;
+	}
 
 	/* Update MAC address with device serial number */
 	mac_addr[0] = 0x00;
@@ -170,19 +161,6 @@ int board_late_init(void)
 		}
 	}
 
-	icicle_mac_addr[0] = '[';
-
-	sprintf(&icicle_mac_addr[1], "%pM", mac_addr);
-
-	icicle_mac_addr[18] = ']';
-	icicle_mac_addr[19] = '\0';
-
-	for (idx = 0; idx < 20; idx++) {
-		if (icicle_mac_addr[idx] == ':')
-			icicle_mac_addr[idx] = ' ';
-	}
-	env_set("icicle_mac_addr0", icicle_mac_addr);
-
 	mac_addr[5] = device_serial_number[0] + 1;
 
 	node = fdt_path_offset(blob, "/soc/ethernet@20110000");
@@ -194,18 +172,33 @@ int board_late_init(void)
 		}
 	}
 
-	icicle_mac_addr[0] = '[';
+	return 0;
+}
 
-	sprintf(&icicle_mac_addr[1], "%pM", mac_addr);
+int ft_board_setup(void *blob, struct bd_info *bd)
+{
+	u32 ret;
+	int node;
 
-	icicle_mac_addr[18] = ']';
-	icicle_mac_addr[19] = '\0';
+	node = fdt_path_offset(blob, "/soc/ethernet@20110000");
+	if (node >= 0) {
+		ret = fdt_setprop(blob, node, "local-mac-address", mac_addr, 6);
+		if (ret) {
+			printf("Error setting local-mac-address property for ethernet@20110000\n");
+			return -ENODEV;
+		}
+	}
+
+	mac_addr[5] -= 1;
 
-	for (idx = 0; idx < 20; idx++) {
-		if (icicle_mac_addr[idx] == ':')
-			icicle_mac_addr[idx] = ' ';
+	node = fdt_path_offset(blob, "/soc/ethernet@20112000");
+	if (node >= 0) {
+		ret = fdt_setprop(blob, node, "local-mac-address", mac_addr, 6);
+		if (ret) {
+			printf("Error setting local-mac-address property for ethernet@20112000\n");
+			return -ENODEV;
+		}
 	}
-	env_set("icicle_mac_addr1", icicle_mac_addr);
 
 	return 0;
 }
diff --git a/board/phytec/phycore_am62ax/phycore_am62ax.env b/board/phytec/phycore_am62ax/phycore_am62ax.env
index 3f4b3cc4f0d..006a817d0e2 100644
--- a/board/phytec/phycore_am62ax/phycore_am62ax.env
+++ b/board/phytec/phycore_am62ax/phycore_am62ax.env
@@ -26,7 +26,11 @@ spi_fdt_addr=0x700000
 spi_image_addr=0x800000
 spi_ramdisk_addr=0x2200000
 
+#ifdef CONFIG_BOOTMETH_RAUC
+bootmeths=rauc script efi extlinux pxe
+#else
 bootmeths=script efi extlinux pxe
+#endif
 boot_targets=mmc1 mmc0 spi_flash dhcp
 
 watchdog=watchdog@e000000
diff --git a/board/phytec/phycore_am62x/phycore_am62x.env b/board/phytec/phycore_am62x/phycore_am62x.env
index 3f4b3cc4f0d..006a817d0e2 100644
--- a/board/phytec/phycore_am62x/phycore_am62x.env
+++ b/board/phytec/phycore_am62x/phycore_am62x.env
@@ -26,7 +26,11 @@ spi_fdt_addr=0x700000
 spi_image_addr=0x800000
 spi_ramdisk_addr=0x2200000
 
+#ifdef CONFIG_BOOTMETH_RAUC
+bootmeths=rauc script efi extlinux pxe
+#else
 bootmeths=script efi extlinux pxe
+#endif
 boot_targets=mmc1 mmc0 spi_flash dhcp
 
 watchdog=watchdog@e000000
diff --git a/board/phytec/phycore_am64x/phycore_am64x.env b/board/phytec/phycore_am64x/phycore_am64x.env
index 3775a27c1a3..bf251c4bcdd 100644
--- a/board/phytec/phycore_am64x/phycore_am64x.env
+++ b/board/phytec/phycore_am64x/phycore_am64x.env
@@ -25,7 +25,11 @@ spi_fdt_addr=0x700000
 spi_image_addr=0x800000
 spi_ramdisk_addr=0x2200000
 
+#ifdef CONFIG_BOOTMETH_RAUC
+bootmeths=rauc script efi extlinux pxe
+#else
 bootmeths=script efi extlinux pxe
+#endif
 boot_targets=mmc1 mmc0 spi_flash dhcp
 
 watchdog=watchdog@e000000
diff --git a/board/phytec/phycore_imx93/spl.c b/board/phytec/phycore_imx93/spl.c
index 7b5d38d438f..beaa536c600 100644
--- a/board/phytec/phycore_imx93/spl.c
+++ b/board/phytec/phycore_imx93/spl.c
@@ -52,8 +52,7 @@ void spl_dram_init(void)
 	int ret;
 	enum phytec_imx93_ddr_eeprom_code ddr_opt = PHYTEC_IMX93_DDR_INVALID;
 
-	/* NOTE: In SPL lpi2c3 is mapped to bus 0 */
-	ret = phytec_eeprom_data_setup(NULL, 0, EEPROM_ADDR);
+	ret = phytec_eeprom_data_setup(NULL, 2, EEPROM_ADDR);
 	if (ret && !IS_ENABLED(CONFIG_PHYCORE_IMX93_RAM_TYPE_FIX))
 		goto out;
 
diff --git a/board/renesas/sparrowhawk/sparrowhawk.c b/board/renesas/sparrowhawk/sparrowhawk.c
index 8e72b5424d1..58de7f25cbd 100644
--- a/board/renesas/sparrowhawk/sparrowhawk.c
+++ b/board/renesas/sparrowhawk/sparrowhawk.c
@@ -6,8 +6,12 @@
 #include <asm/io.h>
 #include <compiler.h>
 #include <dbsc5.h>
+#include <spi.h>
+#include <spi_flash.h>
 #include <spl.h>
 
+#include "../../../drivers/mtd/spi/sf_internal.h"
+
 #if defined(CONFIG_XPL_BUILD)
 
 static const struct renesas_dbsc5_board_config
@@ -112,12 +116,134 @@ dbsc5_get_board_data(struct udevice *dev, const u32 modemr0)
 	 * Use MD[19] setting to discern 8 GiB and 16 GiB DRAM Sparrow Hawk
 	 * board variants from each other automatically.
 	 */
-	if (modemr0 & BIT(19))
+	if ((renesas_get_cpu_rev_integer() >= 3) && (modemr0 & BIT(19)))
 		return &renesas_v4h_sparrowhawk_16g_5500_dbsc5_board_config;
 	else
 		return &renesas_v4h_sparrowhawk_8g_6400_dbsc5_board_config;
 }
 
+static bool renesas_v4h_sparrowhawk_is_evta1 = false;
+
+unsigned int spl_spi_get_uboot_offs(struct spi_flash *flash)
+{
+	const u8 sf_ids_evta1[6] = { 0x01, 0x02, 0x20, 0x4d, 0x00, 0x81 };
+
+	renesas_v4h_sparrowhawk_is_evta1 = !memcmp(sf_ids_evta1, flash->info->id,
+						   sizeof(sf_ids_evta1));
+
+	return CONFIG_SYS_SPI_U_BOOT_OFFS;
+}
+
+void spl_perform_fixups(struct spl_image_info *spl_image)
+{
+	void *blob = spl_image_fdt_addr(spl_image);
+	int err, offs;
+	u32 size;
+
+	if (!renesas_v4h_sparrowhawk_is_evta1)
+		return;
+
+	printf("EVTA1 board detected\n");
+
+	/*
+	 * MicroSD voltage switch is not populated on Sparrow Hawk EVTA1,
+	 * rewrite MicroSD slot regulator to only support 3V3 and disable
+	 * UHS modes in MicroSD slot node.
+	 */
+	if (!blob)
+		return;
+
+	err = fdt_check_header(blob);
+	if (err < 0) {
+		printf("Invalid FDT header: %s\n", fdt_strerror(err));
+		return;
+	}
+
+	size = fdt_totalsize(blob);
+	err = fdt_open_into(blob, blob, size + 64);
+	if (err < 0) {
+		printf("Failed to expand DT\n");
+		return;
+	}
+
+	offs = fdt_path_offset(blob, "/regulator-vcc-sdhi");
+	if (offs < 0) {
+		printf("Failed to locate MicroSD regulator node: %d\n", offs);
+		return;
+	}
+
+	err = fdt_setprop_string(blob, offs, "compatible", "regulator-fixed");
+	if (err < 0) {
+		printf("Failed to set fixed MicroSD regulator: %d\n", err);
+		return;
+	}
+
+	err = fdt_setprop_u32(blob, offs, "regulator-min-microvolt", 3300000);
+	if (err < 0) {
+		printf("Failed to set MicroSD regulator minimum voltage: %d\n", err);
+		return;
+	}
+
+	err = fdt_nop_property(blob, offs, "gpios");
+	if (err < 0) {
+		printf("Failed to remove MicroSD regulator gpios: %d\n", err);
+		return;
+	}
+
+	err = fdt_nop_property(blob, offs, "gpios-states");
+	if (err < 0) {
+		printf("Failed to remove MicroSD regulator gpio states: %d\n", err);
+		return;
+	}
+
+	err = fdt_nop_property(blob, offs, "states");
+	if (err < 0) {
+		printf("Failed to remove MicroSD regulator states: %d\n", err);
+		return;
+	}
+
+	offs = fdt_path_offset(blob, "/soc/mmc@ee140000");
+	if (offs < 0) {
+		printf("Failed to locate MicroSD device node: %d\n", offs);
+		return;
+	}
+
+	err = fdt_nop_property(blob, offs, "sd-uhs-sdr50");
+	if (err < 0) {
+		printf("Failed to disable SDR50 mode in MicroSD node: %d\n", err);
+		return;
+	}
+
+	err = fdt_nop_property(blob, offs, "sd-uhs-sdr104");
+	if (err < 0) {
+		printf("Failed to disable SDR104 mode in MicroSD node: %d\n", err);
+		return;
+	}
+
+	err = fdt_setprop_string(blob, offs, "pinctrl-names", "default");
+	if (err < 0) {
+		printf("Failed to set fixed MicroSD pin names: %d\n", err);
+		return;
+	}
+
+	err = fdt_nop_property(blob, offs, "pinctrl-1");
+	if (err < 0) {
+		printf("Failed to disable UHS pins in MicroSD node: %d\n", err);
+		return;
+	}
+
+	offs = fdt_path_offset(blob, "/soc/pinctrl@e6050000/avb0/pins-vddq18-25-avb");
+	if (offs < 0) {
+		printf("Failed to locate AVB pinctrl node: %d\n", offs);
+		return;
+	}
+
+	err = fdt_setprop_u32(blob, offs, "power-source", 2500);
+	if (err < 0) {
+		printf("Failed to set AVB IO voltage: %d\n", err);
+		return;
+	}
+}
 #endif
 
 #define RST_MODEMR0			0xe6160000
@@ -130,7 +256,7 @@ void renesas_dram_init_banksize(void)
 	int bank;
 
 	/* 8 GiB device, do nothing. */
-	if (!(modemr0 & BIT(19)))
+	if (!((renesas_get_cpu_rev_integer() >= 3) && (modemr0 & BIT(19))))
 		return;
 
 	/* 16 GiB device, adjust memory map. */
diff --git a/board/starfive/visionfive2/visionfive2-i2c-eeprom.c b/board/starfive/visionfive2/visionfive2-i2c-eeprom.c
index 010e386e64d..17a44020bcf 100644
--- a/board/starfive/visionfive2/visionfive2-i2c-eeprom.c
+++ b/board/starfive/visionfive2/visionfive2-i2c-eeprom.c
@@ -275,7 +275,7 @@ static int prog_eeprom(unsigned int size)
 
 	if (is_match_magic()) {
 		printf("MAGIC ERROR, Please check the data@%p.\n", pbuf.buf);
-		return -1;
+		return CMD_RET_FAILURE;
 	}
 
 	ret = i2c_get_chip_for_busnum(CONFIG_SYS_EEPROM_BUS_NUM,
@@ -285,7 +285,7 @@ static int prog_eeprom(unsigned int size)
 	if (ret) {
 		printf("Get i2c bus:%d addr:%d fail.\n", CONFIG_SYS_EEPROM_BUS_NUM,
 		       CONFIG_SYS_I2C_EEPROM_ADDR);
-		return ret;
+		return CMD_RET_FAILURE;
 	}
 
 	for (i = 0, p = (u8 *)pbuf.buf; i < size; ) {
@@ -314,11 +314,11 @@ static int prog_eeprom(unsigned int size)
 	if (ret) {
 		has_been_read = -1;
 		printf("Programming failed.\n");
-		return -1;
+		return CMD_RET_FAILURE;
 	}
 
 	printf("Programming passed.\n");
-	return 0;
+	return CMD_RET_SUCCESS;
 }
 
 /**
diff --git a/board/xilinx/mbv/Kconfig b/board/xilinx/mbv/Kconfig
index c52ba1870b0..68acd8955ae 100644
--- a/board/xilinx/mbv/Kconfig
+++ b/board/xilinx/mbv/Kconfig
@@ -28,7 +28,6 @@ config BOARD_SPECIFIC_OPTIONS
 	imply SPL_RAM_DEVICE
 	imply CMD_SBI
 	imply CMD_PING
-	imply OF_HAS_PRIOR_STAGE
 
 source "board/xilinx/Kconfig"