diff options
| author | Tom Rini <[email protected]> | 2025-05-21 08:59:10 -0600 |
|---|---|---|
| committer | Tom Rini <[email protected]> | 2025-05-21 09:00:21 -0600 |
| commit | 8f85a7345ed5df70a155f0630da72970eb01d87a (patch) | |
| tree | 10acf511e4f955f5874d9e64331c841609b4804a /cmd | |
| parent | 0a87352281ade2b822ce0360e1f105f6e43a96e1 (diff) | |
| parent | ff6e20c32ff33c6963f7d0a79a0914681461f4fa (diff) | |
Merge branch 'master' of https://source.denx.de/u-boot/custodians/u-boot-riscv
CI: https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/26259
- Initial SPL support for T-Head TH1520 SoC
- Improve usability of TH1520 with mainline SPL
- Support building RV32 & RV64 images
- riscv: Improve jh7110 support
Diffstat (limited to 'cmd')
| -rw-r--r-- | cmd/booti.c | 7 |
1 files changed, 5 insertions, 2 deletions
diff --git a/cmd/booti.c b/cmd/booti.c index 1a57fe91397..ced2c1047ab 100644 --- a/cmd/booti.c +++ b/cmd/booti.c @@ -130,8 +130,11 @@ int do_booti(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) bootm_disable_interrupts(); images.os.os = IH_OS_LINUX; - if (IS_ENABLED(CONFIG_RISCV_SMODE)) - images.os.arch = IH_ARCH_RISCV; + if (IS_ENABLED(CONFIG_RISCV)) + if (IS_ENABLED(CONFIG_64BIT)) + images.os.arch = IH_ARCH_RISCV64; + else + images.os.arch = IH_ARCH_RISCV; else if (IS_ENABLED(CONFIG_ARM64)) images.os.arch = IH_ARCH_ARM64; |