diff options
| author | Alif Zakuan Yuslaimi <[email protected]> | 2025-04-16 01:42:12 -0700 |
|---|---|---|
| committer | Tien Fong Chee <[email protected]> | 2025-04-22 11:47:40 +0800 |
| commit | b0dbc9fcb7dfb7522be25ee205997be2fb5e1bdc (patch) | |
| tree | 3af3666f09c900f1448252ecc539771f27adf4ac /configs | |
| parent | 577a60760e1e63a0976b4583c4aa060d81ccfd9e (diff) | |
arch: arm: dts: agilex5: Set SDIO_SEL GPIO pin as output
Use GPIO hogging method in device tree to set SDIO_SEL pin (portb3)
direction as output with value 0 after power-on reset.
This is to ensure stable 0V voltage reading from SDIO_SEL GPIO pin
after board init.
Signed-off-by: Alif Zakuan Yuslaimi <[email protected]>
Reviewed-by: Tien Fong Chee <[email protected]>
Diffstat (limited to 'configs')
| -rw-r--r-- | configs/socfpga_agilex5_defconfig | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/configs/socfpga_agilex5_defconfig b/configs/socfpga_agilex5_defconfig index 79c3f039030..4ac0a5d9b99 100644 --- a/configs/socfpga_agilex5_defconfig +++ b/configs/socfpga_agilex5_defconfig @@ -1,6 +1,7 @@ CONFIG_ARM=y CONFIG_ARCH_SOCFPGA=y CONFIG_TEXT_BASE=0x80200000 +CONFIG_SPL_GPIO=y CONFIG_NR_DRAM_BANKS=3 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80300000 @@ -75,6 +76,8 @@ CONFIG_BOOTFILE="kernel.itb" CONFIG_NET_RANDOM_ETHADDR=y CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_SPL_ALTERA_SDRAM=y +CONFIG_GPIO_HOG=y +CONFIG_SPL_GPIO_HOG=y CONFIG_DWAPB_GPIO=y CONFIG_DM_I2C=y CONFIG_SYS_I2C_DW=y |