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| author | Tom Rini <[email protected]> | 2025-07-31 08:42:06 -0600 |
|---|---|---|
| committer | Tom Rini <[email protected]> | 2025-07-31 08:42:06 -0600 |
| commit | eef444c38994aee9cd3c6e4df5791b5f7209c8d8 (patch) | |
| tree | cea1d9071449690a92258961ca876a42ca0bc739 /configs | |
| parent | 79f3e77133bd7248e4579827effc13f97a32a8a8 (diff) | |
| parent | 4064e7c9fc42c1c376bd919a80b451273472f3df (diff) | |
Merge tag 'u-boot-socfpga-next-20250731' of https://source.denx.de/u-boot/custodians/u-boot-socfpga
This pull request includes updates for the SoCFPGA platform intended for the 2025.10 release
cycle. The highlights focus on enabling the Power Manager for Agilex5, NAND boot support
enhancements, and various bug fixes and cleanups across SoCFPGA components.
CI:
* https://source.denx.de/u-boot/custodians/u-boot-socfpga/-/pipelines/27221
Summary of changes:
Agilex5 Power Manager:
* Initial driver support and DT bindings are added for the Agilex5 Power Manager, enabling
better power domain control.
NAND Boot Support for Agilex5:
* SPL support for NAND boot is enabled.
* UBI/UBIFS support is configured in defconfigs.
* Memory layout updates (malloc and BSS relocation) ensure proper boot behavior.
Code Quality Improvements:
* Coverity and runtime bug fixes (e.g., jtag_usercode check, sub-device conditionals).
* Several cleanup patches addressing formatting, logic, and initialization issues.
General Maintenance:
* SPDX license tags and header include fixes.
* Device tree updates to limit SPI clock frequency and other minor adjustments.
These contributions come from Alif Zakuan Yuslaimi, Andrew Goodbody, Dinesh Maniyam, Naresh
Kumar Ravulapalli, and Tingting Meng.
This patch set has been tested on Agilex 5 devkit.
Diffstat (limited to 'configs')
| -rw-r--r-- | configs/socfpga_agilex5_defconfig | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/configs/socfpga_agilex5_defconfig b/configs/socfpga_agilex5_defconfig index 33a6221979a..cc812c7008c 100644 --- a/configs/socfpga_agilex5_defconfig +++ b/configs/socfpga_agilex5_defconfig @@ -12,7 +12,7 @@ CONFIG_DEFAULT_DEVICE_TREE="socfpga_agilex5_socdk" CONFIG_DM_RESET=y CONFIG_SPL_STACK=0x7d000 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0xbff00000 +CONFIG_SPL_BSS_START_ADDR=0x9ff00000 CONFIG_SPL_BSS_MAX_SIZE=0x100000 CONFIG_SYS_LOAD_ADDR=0x82000000 CONFIG_TARGET_SOCFPGA_AGILEX5_SOCDK=y @@ -42,7 +42,7 @@ CONFIG_HANDOFF=y CONFIG_SPL_HAVE_INIT_STACK=y CONFIG_SPL_SYS_MALLOC=y CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y -CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0xbfa00000 +CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x9fa00000 CONFIG_SPL_SYS_MALLOC_SIZE=0x500000 CONFIG_SPL_CACHE=y CONFIG_SPL_MTD=y @@ -103,3 +103,5 @@ CONFIG_DESIGNWARE_WATCHDOG=y CONFIG_WDT=y # CONFIG_SPL_USE_TINY_PRINTF is not set CONFIG_PANIC_HANG=y +CONFIG_SPL_POWER_DOMAIN=y +CONFIG_AGILEX5_PMGR_POWER_DOMAIN=y |