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| author | Michal Simek <[email protected]> | 2026-07-30 08:49:17 +0200 |
|---|---|---|
| committer | Michal Simek <[email protected]> | 2026-08-12 06:55:15 +0200 |
| commit | f2294a98b28627b7b2075d5d19d2909de6b27667 (patch) | |
| tree | 374da9f91172070d2177b9762daab7c0b24b17d6 /contrib/apps/httpserver/README | |
| parent | 9e8a0f54b0231d11e481fbf7832a8780e6201b71 (diff) | |
xilinx: versal2: Clean UFS firmware interface
The M-PHY and SRAM readiness poll loops move out of the UFS controller
driver and into the firmware backend, exposed as blocking waits with
a caller-owned timeout budget. This keeps the UFS driver backend-agnostic
and lets an other backends offload the wait to the platform in a single
call instead of round-tripping every poll.
set_sram_bypass() now performs the SRAM_CSR read-modify-write in the
firmware layer.
Hook up functions are also update to reflect their usage.
Signed-off-by: Michal Simek <[email protected]>
Link: https://patch.msgid.link/26bc9aa2c02921690e126ab3401f7974ef04ad6e.1785394153.git.michal.simek@amd.com
Diffstat (limited to 'contrib/apps/httpserver/README')
0 files changed, 0 insertions, 0 deletions