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authorPratyush Yadav <[email protected]>2024-06-04 11:39:10 +0530
committerTom Rini <[email protected]>2024-06-12 18:40:37 -0600
commit11d5655919ab94f4452f45f1a1b38a6a30030705 (patch)
tree13a736479f6684d4af4d7d585640c9a44307b3ce /doc/develop/bootstd/script.rst
parent15d0dcc0ec1f424199dff2a3cbe037bc3a7d8749 (diff)
mtd: spi-nor-core: Do not start or end writes at odd address in DTR mode
On DTR capable flashes like Micron Xcella the writes cannot start or end at an odd address in DTR mode. Extra 0xff bytes need to be prepended or appended respectively to make sure both the start and end addresses are even. Signed-off-by: Pratyush Yadav <[email protected]> Signed-off-by: Apurva Nandan <[email protected]> Signed-off-by: Vignesh Raghavendra <[email protected]> Tested-by: Jonathan Humphreys <[email protected]> Signed-off-by: Manorit Chawdhry <[email protected]>
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