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| author | Jonas Schwöbel <[email protected]> | 2025-03-04 09:02:11 +0200 |
|---|---|---|
| committer | Svyatoslav Ryhel <[email protected]> | 2025-03-11 17:39:52 +0200 |
| commit | dbc27c2462871722fe9ee591a0e7cdba6d5f48b9 (patch) | |
| tree | 1ebe802fb2be793b4318badd06dfd157ad1125ad /doc/develop/bootstd | |
| parent | 8fb7ed59a8fa6d73a5d4ee9ec65c521de3ed1f21 (diff) | |
ARM: tegra: clock: fix PLLD/PLLD2 related clock calculations
While PLLD/D2 is the nominal parent clock, all derived clocks are generated
from its single output, plld_out0, which is PLLD/D2 divided by two. Direct
use of PLLD/D2 is absent in peripheral clock configurations. Therefore,
clock derivation formulas must take in account this division.
Signed-off-by: Jonas Schwöbel <[email protected]>
Signed-off-by: Svyatoslav Ryhel <[email protected]>
Diffstat (limited to 'doc/develop/bootstd')
0 files changed, 0 insertions, 0 deletions