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| author | Bin Meng <[email protected]> | 2021-06-15 13:45:57 +0800 |
|---|---|---|
| committer | Leo Yu-Chi Liang <[email protected]> | 2021-06-17 09:39:46 +0800 |
| commit | 62ce0a02f9e5bda51a05c5f735e5a75f6c4bbb54 (patch) | |
| tree | 086819c8f5cbcab23e7932ab7d9aa747d3aed8e1 /doc/develop/driver-model/debugging.rst | |
| parent | 279de759bd2ceb1dad6ff30c7d27c8ff9c5706a3 (diff) | |
riscv: andes_plic: Fix riscv_get_ipi() mask
Current logic in riscv_get_ipi() for Andes PLICSW does not look
correct. The mask to test IPI pending bits for a hart should be
left shifted by (8 * gd->arch.boot_hart), just the same as what
is done in riscv_send_ipi().
Fixes: 8b3e97badf97 ("riscv: add functions for reading the IPI status")
Signed-off-by: Bin Meng <[email protected]>
Reviewed-by: Rick Chen <[email protected]>
Tested-by: Rick Chen <[email protected]>
Diffstat (limited to 'doc/develop/driver-model/debugging.rst')
0 files changed, 0 insertions, 0 deletions