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| author | Michal Simek <[email protected]> | 2022-01-06 09:49:41 +0100 |
|---|---|---|
| committer | Michal Simek <[email protected]> | 2022-01-12 10:41:46 +0100 |
| commit | 1d78d68349621316ddff95a0d0d3ab9360061a9a (patch) | |
| tree | 9e7a79af52c574793ef732d006f00b34c31d7cb7 /doc/develop/python_cq.rst | |
| parent | 28880b68d4e4760ebe54806eeff49ff61961ff8e (diff) | |
phy: zynqmp: Add serdes/psgtr driver
Add PSGTR driver for Xilinx ZynqMP.
The most of configurations are taken from Linux kernel psgtr driver.
USB3.0 and SGMII configurations are tested on SOM. In SGMII case also
IOU_SLCR reg is updated to get proper clock setup and signal detection
configuration.
Signed-off-by: Michal Simek <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
Link: https://lore.kernel.org/r/36e6e9d3baf8511af1916e91e4887032ca2b6c20.1641458978.git.michal.simek@xilinx.com
Diffstat (limited to 'doc/develop/python_cq.rst')
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