diff options
| author | Pali Rohár <[email protected]> | 2022-08-01 15:31:44 +0200 |
|---|---|---|
| committer | Peng Fan <[email protected]> | 2022-09-06 14:08:33 +0800 |
| commit | 27b2bff6eb18dfb5ba58f68b79fdc57d72c6d2a3 (patch) | |
| tree | d577b2e3c3c98b5ac26902918adcb796b4c01d47 /doc/develop/python_cq.rst | |
| parent | 1f90be6f3445f72c526f7396f4f4a53bb7a097aa (diff) | |
board: freescale: p1_p2_rdb_pc: Add workaround for non-working watchdog
If watchdog timer was already set to non-disabled value then it means that
watchdog timer was already activated, has already expired and caused CPU
reset. If this happened then due to CPLD firmware bug, writing to wd_cfg
register has no effect and therefore it is not possible to reactivate
watchdog timer again. Watchdog starts working again after CPU reset via
non-watchdog method.
Implement this workaround (reset CPU when it was reset by watchdog) to make
watchdog usable again. Watchdog timer logic on these P1/P2 RDB boards is
connected to CPLD, not to SoC itself.
Note that reset does not occur immediately after calling do_reset(), but
after few ms later as real reset is done by CPLD. So it is normal that
function do_reset() returns. Therefore hangs after calling do_reset() to
prevent CPU execution of the rest U-Boot code.
Signed-off-by: Pali Rohár <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
Diffstat (limited to 'doc/develop/python_cq.rst')
0 files changed, 0 insertions, 0 deletions