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| author | Tom Rini <[email protected]> | 2024-09-10 07:50:05 -0600 |
|---|---|---|
| committer | Tom Rini <[email protected]> | 2024-09-10 07:50:05 -0600 |
| commit | 40727391702a1a48c58b0a3c6e69013ff8af6cb2 (patch) | |
| tree | 84b20693c9f3dd5d5cc831d0b999bd5523523c35 /doc/develop/python_cq.rst | |
| parent | aded8e4aaee1efa32f2ce7e3c45205f523afc2da (diff) | |
| parent | 1806fed0ce6b56365ecf6b84ce6d17aafd3af979 (diff) | |
Merge https://gitlab.denx.de/u-boot/custodians/u-boot-riscv
CI: https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/22292
- Add rdcycle to RISC-V exception command
- Some fixes and refactoring
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