video: tegra20: dc: configure behavior if PLLD/D2 is used

If DISP1 is a PLLD/D2 child, it cannot go over 370MHz. The cause
of this is not quite clear. This can be overcomed by further
halving the PLLD/D2 if the target parent rate is over 800MHz.
This way DISP1 and DSI clocks will have the same frequency. The
shift divider in this case has to be calculated from the
original PLLD/D2 frequency and is passed from the DSI driver.

Tested-by: Andreas Westman Dorcsak <[email protected]> # ASUS Grouper E1565
Tested-by: Ion Agorria <[email protected]> # HTC One X
Tested-by: Svyatoslav Ryhel <[email protected]> # Nvidia Tegratab T114
Tested-by: Jonas Schwöbel <[email protected]> # Microsoft Surface 2
Signed-off-by: Jonas Schwöbel <[email protected]>
Signed-off-by: Svyatoslav Ryhel <[email protected]>
Acked-by: Thierry Reding <[email protected]>

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