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| author | Yann Gautier <[email protected]> | 2022-09-13 13:23:44 +0200 |
|---|---|---|
| committer | Jaehoon Chung <[email protected]> | 2022-10-24 18:01:59 +0900 |
| commit | be1872982e425375a7da6ac75da946f9d15df405 (patch) | |
| tree | 9e59c53825a634b7e721265f7464613f2d590cd2 /doc/develop/python_cq.rst | |
| parent | 12fc8efe5ad3d57ee82e0a4c548f5c47f473a9b4 (diff) | |
mmc: stm32_sdmmc2: add dual data rate support
To support dual data rate with STM32 sdmmc2 driver, the dedicated bit
(DDR - BIT(18)) needs to be set in the CLKRC register. Clock bypass
(no divider) is not allowed in this case. This is required for the
eMMC DDR modes.
Signed-off-by: Yann Gautier <[email protected]>
Reviewed-by: Jaehoon Chung <[email protected]>
Diffstat (limited to 'doc/develop/python_cq.rst')
0 files changed, 0 insertions, 0 deletions