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| author | Andre Przywara <[email protected]> | 2022-07-03 00:14:24 +0100 |
|---|---|---|
| committer | Andre Przywara <[email protected]> | 2023-10-22 23:41:52 +0100 |
| commit | beeace9ba1689e6eaba8d286f885a5f0e973b26e (patch) | |
| tree | 8f2ea3aab963a09a96982f86128089a986db7c6f /doc/develop/python_cq.rst | |
| parent | 5b7c58fbba568808791b636e4ee23e2348e58c0b (diff) | |
sunxi: refactor serial base addresses to avoid asm/arch/cpu.h
At the moment we have each SoC's memory map defined in its own cpu.h,
which is included in include/configs/sunxi_common.h. This will be a
problem with the introduction of Allwinner RISC-V support.
Remove the inclusion of that header file from the common config header,
instead move the required serial base addresses (for the SPL) into a
separate header file. Then include the original cpu.h file only where
we really need it, which is only under arch/arm now.
This disentangles the architecture specific header files from the
generic code.
Signed-off-by: Andre Przywara <[email protected]>
Diffstat (limited to 'doc/develop/python_cq.rst')
0 files changed, 0 insertions, 0 deletions
