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| author | Neil Armstrong <[email protected]> | 2024-09-30 14:44:24 +0200 |
|---|---|---|
| committer | Neil Armstrong <[email protected]> | 2024-10-14 08:55:28 +0200 |
| commit | c64d22b57d8a9fe4d08ab677ba33d6004b98a468 (patch) | |
| tree | 1a1403a5a9ba4504df76213a9e6a2d13a9859af5 /doc/develop/python_cq.rst | |
| parent | 9c223d8d8b8fbad667971f36eabe203480a8c39b (diff) | |
ufs: fix dcache flush and invalidate range calculation
The current calculation will omit doing a flush/invalidate on the last
cacheline if the base address is not aligned with DMA_MINALIGN.
This causes commands failures and write corruptions on Qualcomm
platforms.
Reviewed-by: Neha Malcom Francis <[email protected]>
Tested-by: Venkatesh Yadav Abbarapu <[email protected]>
Tested-by: Julius Lehmann <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Neil Armstrong <[email protected]>
Diffstat (limited to 'doc/develop/python_cq.rst')
0 files changed, 0 insertions, 0 deletions