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| author | Ovidiu Panait <[email protected]> | 2022-02-13 10:09:24 +0200 |
|---|---|---|
| committer | Michal Simek <[email protected]> | 2022-02-15 13:11:43 +0100 |
| commit | d1114b83405ceaccd46bce96001e6da4fab3ae40 (patch) | |
| tree | 8ff14c919f2cdf9625c279b1e914b9a19ff630bd /doc/develop/python_cq.rst | |
| parent | 339f489d524e8daa40a4ab0c64bfe65ef30f5fc6 (diff) | |
microblaze: exception: fix unaligned data access register mask
The correct mask for getting the source/destination register from ESR in
the case of an unaligned access exception is 0x3E0. With this change, a
dummy unaligned store produces the expected info:
"""
>> swi r5, r0, 0x111
...
Hardware exception at 0x111 address
Unaligned data access exception
Unaligned word access
Unaligned store access
Register R5
Return address from exception 0x7f99dfc
### ERROR ### Please RESET the board ###
"""
Signed-off-by: Ovidiu Panait <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Michal Simek <[email protected]>
Diffstat (limited to 'doc/develop/python_cq.rst')
0 files changed, 0 insertions, 0 deletions