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| author | Bryan Brattlof <[email protected]> | 2026-01-28 18:06:21 +0530 |
|---|---|---|
| committer | Tom Rini <[email protected]> | 2026-02-07 15:53:13 -0600 |
| commit | da6d5a93ddac5e60ebc84c75456318fa20a8f995 (patch) | |
| tree | cba39663cf250cc9f27b4fa78e95a1eb3c53df70 /doc/develop/python_cq.rst | |
| parent | c9d1fe757df659338a84c9524c9bfb0545aa1bee (diff) | |
arm: mach-k3: r5: j721e: clk-data: manually set the main_pll3 frequency
Moving forward, DM firmware will no longer mess with the MAIN_PLL3.
This means MAIN_PLL3 will need to be manually set to 2GHz in order for
the CPSW9G HSDIV to have the correct 250MHz output for RGMII.
Signed-off-by: Bryan Brattlof <[email protected]>
Signed-off-by: Siddharth Vadapalli <[email protected]>
Diffstat (limited to 'doc/develop/python_cq.rst')
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