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| author | Tien Fong Chee <[email protected]> | 2022-04-27 12:27:21 +0800 |
|---|---|---|
| committer | Tien Fong Chee <[email protected]> | 2022-06-16 16:10:44 +0800 |
| commit | ee06c5390f2f1e2f1bc23e14a7cd8665c1e42ff4 (patch) | |
| tree | fb14185e5c4c674453af6f93ec7d18a12ef5b878 /doc/develop/python_cq.rst | |
| parent | f70e00fa7da69d16379c0b3526b793be45cd055d (diff) | |
ddr: altera: Ignore bit[7-4] for both seq2core & core2seq handshake in HPS
Bit[7-4] for both register seq2core and core2seq handshake in HPS are not
required for triggering DDR re-calibration or resetting EMIF. So, ignoring
these bits just for playing it safe.
Signed-off-by: Tien Fong Chee <[email protected]>
Diffstat (limited to 'doc/develop/python_cq.rst')
0 files changed, 0 insertions, 0 deletions