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| author | Michal Simek <[email protected]> | 2023-09-27 11:53:33 +0200 |
|---|---|---|
| committer | Michal Simek <[email protected]> | 2023-10-09 12:12:30 +0200 |
| commit | fa822ad19e97af1176212f0f9f980f8061a39572 (patch) | |
| tree | 2677efc4bf6fa9adedc2cf685c903c0dc1a5e277 /doc/develop/python_cq.rst | |
| parent | 64f5e3b4924781890c6913fd2537563df28b1ced (diff) | |
arm64: zynqmp: Add support for SC revC
System controller revC is using ADI ethernet phy instead of TI because of
supply chain issues.
Describe reset assert and de-assert times to 10us and 5ms respectively
according to the datasheet. Also setup RGMII RX and TX delay values to
2400ps as per board bring up observations.
Signed-off-by: Michal Simek <[email protected]>
Link: https://lore.kernel.org/r/2790f6cede7485556d581ab8270dda477fa21522.1695808407.git.michal.simek@amd.com
Diffstat (limited to 'doc/develop/python_cq.rst')
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