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| author | Svyatoslav Ryhel <[email protected]> | 2024-12-13 16:53:18 +0200 |
|---|---|---|
| committer | Tom Rini <[email protected]> | 2024-12-16 17:07:39 -0600 |
| commit | 1db256a3473645ed12de980355f6089baf544bf4 (patch) | |
| tree | d1cb1e3b615410e9c01a2d42316490f9c7802a8a /doc/develop | |
| parent | e46fe0daf3f9ac486079bac818d24548716c5847 (diff) | |
driver: clk: tegra: partially support PLL clocks
Return PLL id into struct clk if PLL is parsed from device
tree instead of throwing an error. Allow requesting PLL
clock rate via get_rate op.
Signed-off-by: Svyatoslav Ryhel <[email protected]>
Diffstat (limited to 'doc/develop')
0 files changed, 0 insertions, 0 deletions