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| author | Andre Przywara <[email protected]> | 2024-02-12 23:13:01 +0000 |
|---|---|---|
| committer | Andre Przywara <[email protected]> | 2024-10-10 00:23:41 +0100 |
| commit | 7db2f11eb041043d43fe4dd1879d567d33759ee0 (patch) | |
| tree | 2cdfacb958caf47a8298a8ab683ffcab6a918f58 /doc/develop | |
| parent | 9c4b44d1e3e988b3db6a631c436498e186297b31 (diff) | |
clk: sunxi: a80: Fix reset description
Clock gates and reset lines share a common structure in the sunxi clock
driver descriptions, but use different flags to tell them apart.
The description of the Allwinner A80 MMC clock reset lines was
erroneously using the "GATE" macro, which made the reset driver ignore
that entry, complaining with:
sunxi_set_reset: (RST-reset:#0) unhandled
Change that to the correct "RESET" macro, to make the reset driver
happy.
Fixes e0c7ce7e52b7 ("sunxi: clk: A80: add MMC clock support")
Signed-off-by: Andre Przywara <[email protected]>
Diffstat (limited to 'doc/develop')
0 files changed, 0 insertions, 0 deletions