doc: stm32mp1: add page for device tree bindings

With device tree binding migration to yaml it is difficult to synchronize
the binding from Linux kernel to U-Boot.

Instead of maintaining the same dt bindings, this patch adds in the U-Boot
documentation the path to the device tree bindings in Linux kernel for
STMicroelectronics devices, when they are used without modification.

Signed-off-by: Patrick Delaunay <[email protected]>
Signed-off-by: Patrice Chotard <[email protected]>

Add links for referenced text files.
Signed-off-by: Heinrich Schuchardt <[email protected]>

2 files changed, 0 insertions, 247 deletions

diff --git a/doc/device-tree-bindings/clock/st,stm32-rcc.txt b/doc/device-tree-bindings/clock/st,stm32-rcc.txt
deleted file mode 100644
index 0532d815dae..00000000000
--- a/doc/device-tree-bindings/clock/st,stm32-rcc.txt
+++ /dev/null
@@ -1,95 +0,0 @@
-STMicroelectronics STM32 Reset and Clock Controller
-===================================================
-
-The RCC IP is both a reset and a clock controller.
-
-Please refer to clock-bindings.txt for common clock controller binding usage.
-Please also refer to reset.txt for common reset controller binding usage.
-
-Required properties:
-- compatible: Should be:
-  "st,stm32f42xx-rcc"
-  "st,stm32f469-rcc"
-- reg: should be register base and length as documented in the
-  datasheet
-- #reset-cells: 1, see below
-- #clock-cells: 2, device nodes should specify the clock in their "clocks"
-  property, containing a phandle to the clock device node, an index selecting
-  between gated clocks and other clocks and an index specifying the clock to
-  use.
-
-Example:
-
-	rcc: rcc@40023800 {
-		#reset-cells = <1>;
-		#clock-cells = <2>
-		compatible = "st,stm32f42xx-rcc", "st,stm32-rcc";
-		reg = <0x40023800 0x400>;
-	};
-
-Specifying gated clocks
-=======================
-
-The primary index must be set to 0.
-
-The secondary index is the bit number within the RCC register bank, starting
-from the first RCC clock enable register (RCC_AHB1ENR, address offset 0x30).
-
-It is calculated as: index = register_offset / 4 * 32 + bit_offset.
-Where bit_offset is the bit offset within the register (LSB is 0, MSB is 31).
-
-To simplify the usage and to share bit definition with the reset and clock
-drivers of the RCC IP, macros are available to generate the index in
-human-readble format.
-
-For STM32F4 series, the macro are available here:
- - include/dt-bindings/mfd/stm32f4-rcc.h
-
-Example:
-
-	/* Gated clock, AHB1 bit 0 (GPIOA) */
-	... {
-		clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOA)>
-	};
-
-	/* Gated clock, AHB2 bit 4 (CRYP) */
-	... {
-		clocks = <&rcc 0 STM32F4_AHB2_CLOCK(CRYP)>
-	};
-
-Specifying other clocks
-=======================
-
-The primary index must be set to 1.
-
-The secondary index is bound with the following magic numbers:
-
-	0	SYSTICK
-	1	FCLK
-
-Example:
-
-	/* Misc clock, FCLK */
-	... {
-		clocks = <&rcc 1 STM32F4_APB1_CLOCK(TIM2)>
-	};
-
-
-Specifying softreset control of devices
-=======================================
-
-Device nodes should specify the reset channel required in their "resets"
-property, containing a phandle to the reset device node and an index specifying
-which channel to use.
-The index is the bit number within the RCC registers bank, starting from RCC
-base address.
-It is calculated as: index = register_offset / 4 * 32 + bit_offset.
-Where bit_offset is the bit offset within the register.
-For example, for CRC reset:
-  crc = AHB1RSTR_offset / 4 * 32 + CRCRST_bit_offset = 0x10 / 4 * 32 + 12 = 140
-
-example:
-
-	timer2 {
-		resets	= <&rcc STM32F4_APB1_RESET(TIM2)>;
-	};
diff --git a/doc/device-tree-bindings/clock/st,stm32h7-rcc.txt b/doc/device-tree-bindings/clock/st,stm32h7-rcc.txt
deleted file mode 100644
index 9d4b5873d9f..00000000000
--- a/doc/device-tree-bindings/clock/st,stm32h7-rcc.txt
+++ /dev/null
@@ -1,152 +0,0 @@
-STMicroelectronics STM32H7 Reset and Clock Controller
-=====================================================
-
-The RCC IP is both a reset and a clock controller.
-
-Please refer to clock-bindings.txt for common clock controller binding usage.
-Please also refer to reset.txt for common reset controller binding usage.
-
-Required properties:
-- compatible: Should be:
-  "st,stm32h743-rcc"
-
-- reg: should be register base and length as documented in the
-  datasheet
-
-- #reset-cells: 1, see below
-
-- #clock-cells : from common clock binding; shall be set to 1
-
-- clocks: External oscillator clock phandle
-  - high speed external clock signal (HSE)
-  - low speed external clock signal (LSE)
-  - external I2S clock (I2S_CKIN)
-
-- st,syscfg: phandle for pwrcfg, mandatory to disable/enable backup domain
-  write protection (RTC clock).
-
-- pll x node: Allow to register a pll with specific parameters.
-  Please see PLL section below.
-
-Example:
-
-	rcc: rcc@58024400 {
-		#reset-cells = <1>;
-		#clock-cells = <2>
-		compatible = "st,stm32h743-rcc", "st,stm32-rcc";
-		reg = <0x58024400 0x400>;
-		clocks = <&clk_hse>, <&clk_lse>, <&clk_i2s_ckin>;
-
-		st,syscfg = <&pwrcfg>;
-
-		#address-cells = <1>;
-		#size-cells = <0>;
-
-		vco1@58024430 {
-			#clock-cells = <0>;
-			compatible = "stm32,pll";
-			reg = <0>;
-		};
-
-		vco2@58024438 {
-			#clock-cells = <0>;
-			compatible = "stm32,pll";
-			reg = <1>;
-			st,clock-div = <2>;
-			st,clock-mult = <40>;
-			st,frac-status = <0>;
-			st,frac = <0>;
-			st,vcosel = <1>;
-			st,pllrge = <2>;
-		};
-	};
-
-
-STM32H7 PLL
------------
-
-The VCO of STM32 PLL could be reprensented like this:
-
-  Vref    ---------       --------
-    ---->| / DIVM  |---->| x DIVN | ------> VCO
-          ---------       --------
-		             ^
-			     |
-	                  -------
-		         | FRACN |
-		          -------
-
-When the PLL is configured in integer mode:
-- VCO = ( Vref / DIVM ) * DIVN
-
-When the PLL is configured in fractional mode:
-- VCO = ( Vref / DIVM ) * ( DIVN + FRACN / 2^13)
-
-
-Required properties for pll node:
-- compatible: Should be:
-  "stm32,pll"
-
-- #clock-cells: from common clock binding; shall be set to 0
-- reg: Should be the pll number.
-
-Optional properties:
-- st,clock-div:  DIVM division factor       : <1..63>
-- st,clock-mult: DIVN multiplication factor : <4..512>
-
-- st,frac-status:
-   - 0 Pll is configured in integer mode
-   - 1 Pll is configure in fractional mode
-
-- st,frac: Fractional part of the multiplication factor : <0..8191>
-
-- st,vcosel: VCO selection
-  - 0: Wide VCO range:192 to 836 MHz
-  - 1: Medium VCO range:150 to 420 MHz
-
-- st,pllrge: PLL input frequency range
-  - 0: The PLL input (Vref / DIVM) clock range frequency is between 1 and 2 MHz
-  - 1: The PLL input (Vref / DIVM) clock range frequency is between 2 and 4 MHz
-  - 2: The PLL input (Vref / DIVM) clock range frequency is between 4 and 8 MHz
-  - 3: The PLL input (Vref / DIVM) clock range frequency is between 8 and 16 MHz
-
-
-The peripheral clock consumer should specify the desired clock by
-having the clock ID in its "clocks" phandle cell.
-
-All available clocks are defined as preprocessor macros in
-dt-bindings/clock/stm32h7-clks.h header and can be used in device
-tree sources.
-
-Example:
-
-		timer5: timer@40000c00 {
-			compatible = "st,stm32-timer";
-			reg = <0x40000c00 0x400>;
-			interrupts = <50>;
-			clocks = <&rcc TIM5_CK>;
-
-		};
-
-Specifying softreset control of devices
-=======================================
-
-Device nodes should specify the reset channel required in their "resets"
-property, containing a phandle to the reset device node and an index specifying
-which channel to use.
-The index is the bit number within the RCC registers bank, starting from RCC
-base address.
-It is calculated as: index = register_offset / 4 * 32 + bit_offset.
-Where bit_offset is the bit offset within the register.
-
-For example, for CRC reset:
-  crc = AHB4RSTR_offset / 4 * 32 + CRCRST_bit_offset = 0x88 / 4 * 32 + 19 = 1107
-
-All available preprocessor macros for reset are defined dt-bindings//mfd/stm32h7-rcc.h
-header and can be used in device tree sources.
-
-example:
-
-	timer2 {
-		resets	= <&rcc STM32H7_APB1L_RESET(TIM2)>;
-	};