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| author | Tom Rini <[email protected]> | 2022-04-05 13:45:22 -0400 |
|---|---|---|
| committer | Tom Rini <[email protected]> | 2022-04-05 13:45:22 -0400 |
| commit | 59bffec43a657598b194b9eb30dc01eec06078c7 (patch) | |
| tree | 80a668bc14a348be6be49a9808e811a7f4bb82c4 /doc/device-tree-bindings/memory-controller | |
| parent | 037ef53cf01c522073a0a930c84c3ca858f032e1 (diff) | |
| parent | da61ee662554f98fac0ab19c6b893edd82edb098 (diff) | |
Merge branch '2022-04-04-platform-updates'
- Updates for exynos78x0 and TI K3 platforms
Diffstat (limited to 'doc/device-tree-bindings/memory-controller')
| -rw-r--r-- | doc/device-tree-bindings/memory-controller/k3-j721e-ddrss.txt | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/doc/device-tree-bindings/memory-controller/k3-j721e-ddrss.txt b/doc/device-tree-bindings/memory-controller/k3-j721e-ddrss.txt index dd0260b3940..df3290a6b9d 100644 --- a/doc/device-tree-bindings/memory-controller/k3-j721e-ddrss.txt +++ b/doc/device-tree-bindings/memory-controller/k3-j721e-ddrss.txt @@ -13,6 +13,7 @@ Required properties: "ti,am64-ddrss" for am642 - reg-names cfg - Map the controller configuration region ctrl_mmr_lp4 - Map LP4 register region in ctrl mmr + ss - Map the DDRSS configuration region - reg: Contains the register map per reg-names. - power-domains: Should contain two entries: - an entry to TISCI DDR CFG device @@ -32,6 +33,13 @@ Required properties: - ti,pi-data: An array containing the phy independent block settings - ti,phy-data: An array containing the ddr phy settings. +Optional properties: +-------------------- +- reg-names ss - Map the DDRSS configuration region +- reg: Must add "ss" to list if the above ss region is included. +- ti,ecc-enable: Boolean flag to enable ECC. This will reduce available DDR + by 1/9. + Example (J721E): ================ |