Merge branch 'next'

Note that this undoes the changes of commit cf6d4535cc4c ("x86:
emulation: Disable bloblist for now") as that was intended only for the
release due to time.

2 files changed, 171 insertions, 0 deletions

diff --git a/doc/device-tree-bindings/mtd/cadence,nand.yaml b/doc/device-tree-bindings/mtd/cadence,nand.yaml
new file mode 100644
index 00000000000..11ce023ec64
--- /dev/null
+++ b/doc/device-tree-bindings/mtd/cadence,nand.yaml
@@ -0,0 +1,98 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/mtd/cadence,nand.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Cadence NAND controller
+
+maintainers:
+  - Dinesh Maniyam <[email protected]>
+
+properties:
+  compatible:
+    enum:
+      - cdns,nand
+
+  reg-names:
+    description: |
+      There are two register regions:
+        reg:  register interface
+        sdma: host data/command interface
+    items:
+      - const: reg
+      - const: sdma
+
+  reg:
+    minItems: 2
+    maxItems: 2
+
+  interrupts:
+    maxItems: 1
+
+  clocks:
+    description: |
+      There is one controller core clock
+    maxItems: 1
+
+  resets:
+    description: |
+      There are two resets:
+        controller core reset
+        combo-phy register reset
+    minItems: 1
+    maxItems: 2
+
+  cdns,board-delay-ps:
+     description: |
+        Estimated Board delay. The value includes the total
+        round trip delay for the signals and is used for deciding on values
+        associated with data read capture. The example formula for SDR mode is
+        the following:
+        board delay = RE#PAD delay + PCB trace to device + PCB trace from device
+        + DQ PAD delay
+     enum:
+       - 4830
+
+patternProperties:
+  "^nand@[a-f0-9]$":
+    type: object
+    properties:
+      compatible:
+        const: cdns,nand
+
+      reg:
+        maxItems: 1
+
+      label:
+        maxItems: 1
+
+required:
+  - compatible
+  - reg
+  - interrupts
+  - clocks
+  - cdns,board-delay-ps
+
+unevaluatedProperties: false
+
+examples:
+  - |
+    nand-controller@60000000 {
+        compatible = "cdns,nand";
+        reg = <0x60000000 0x10000>, <0x80000000 0x1000>;
+        reg-names = "reg", "sdma";
+        #address-cells = <1>;
+        #size-cells = <0>;
+        clocks = <&clk>;
+        cdns,board-delay-ps = <4830>;
+        interrupts = <2 0>;
+        nand@0 {
+            label = "nand-0";
+            reg = <0>;
+        };
+        nand@1 {
+            label = "nand-1";
+            reg = <1>;
+        };
+    };
diff --git a/doc/device-tree-bindings/pinctrl/adi,adsp-pinctrl.yaml b/doc/device-tree-bindings/pinctrl/adi,adsp-pinctrl.yaml
new file mode 100644
index 00000000000..418ebd5ce41
--- /dev/null
+++ b/doc/device-tree-bindings/pinctrl/adi,adsp-pinctrl.yaml
@@ -0,0 +1,73 @@
+# SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pinctrl/adi,adsp-pinctrl.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Pinctrl Driver for Analog Devices SC5xx Processors
+
+maintainers:
+  - Vasileios Bimpikas <[email protected]>
+  - Utsav Agarwal <[email protected]>
+  - Arturs Artamonovs <[email protected]>
+
+description: |
+  This driver provides an interface for performing pin configuration
+  Analog Devices SoCs using the ADSP PORT hardware for pin
+  configuration according to the HRM. Currently this is only the
+  SC5xx series.
+
+properties:
+  compatible:
+    const: adi,adsp-pinctrl
+
+  reg:
+    maxItems: 1
+
+  adi,npins:
+    $ref: /schemas/types.yaml#/definitions/uint32
+    description:
+      Total number of pins available to this SoC's pin controller,
+      found in the HRM.
+
+patternProperties:
+  '_pins$':
+    type: object
+
+    properties:
+      adi,pins:
+        $ref: /schemas/types.yaml#/definitions/uint32-array
+        description:
+          For n pins, 2n values must be provided as a sequence of pin
+          name as identified with the ADI_ADSP_PIN() macro and a pin
+          function constant, both defined in
+          include/dt-bindings/pinctrl/adi-adsp.h.
+
+    required:
+     - adi,pins
+
+    additionalProperties: false
+
+required:
+  - compatible
+  - reg
+  - adi,npins
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/pinctrl/adi-adsp.h>
+
+    soc {
+      pinctrl0: pinctrl@0x31004000 {
+        compatible = "adi,adsp-pinctrl";
+        reg = <0x31004000 0x500>;
+        adi,npins = <135>;
+        uart0_default: uart0_pins {
+          adi,pins = <ADI_ADSP_PIN('A', 6) ADI_ADSP_PINFUNC_ALT1>,
+                     <ADI_ADSP_PIN('A', 7) ADI_ADSP_PINFUNC_ALT1>;
+        };
+      };
+
+    };