Merge tag 'v2024.07-rc4' into next

Prepare v2024.070-rc4

6 files changed, 205 insertions, 470 deletions

diff --git a/doc/board/rockchip/rockchip.rst b/doc/board/rockchip/rockchip.rst
index 9a726e9cde6..cfbf641f494 100644
--- a/doc/board/rockchip/rockchip.rst
+++ b/doc/board/rockchip/rockchip.rst
@@ -104,6 +104,7 @@ List of mainline supported Rockchip boards:
      - Pine64 SOQuartz on Blade (soquartz-blade-rk3566)
      - Pine64 SOQuartz on CM4-IO (soquartz-cm4-rk3566)
      - Pine64 SOQuartz on Model A (soquartz-model-a-rk3566)
+     - Powkiddy X55 (powkiddy-x55-rk3566)
      - Radxa CM3 IO Board (radxa-cm3-io-rk3566)
 
 * rk3568
@@ -123,6 +124,7 @@ List of mainline supported Rockchip boards:
      - Edgeble Neural Compute Module 6B SoM - Neu6b (neu6b-io-rk3588)
      - FriendlyElec NanoPC-T6 (nanopc-t6-rk3588)
      - Generic RK3588S/RK3588 (generic-rk3588)
+     - Indiedroid Nova (nova-rk3588s)
      - Pine64 QuartzPro64 (quartzpro64-rk3588)
      - Radxa ROCK 5A (rock5a-rk3588s)
      - Radxa ROCK 5B (rock5b-rk3588)
diff --git a/doc/board/starfive/index.rst b/doc/board/starfive/index.rst
index d369b986ccd..72ab6ddfbf6 100644
--- a/doc/board/starfive/index.rst
+++ b/doc/board/starfive/index.rst
@@ -8,4 +8,5 @@ StarFive
 
    milk-v_mars
    milk-v_mars_cm
+   pine64_star64
    visionfive2
diff --git a/doc/board/starfive/pine64_star64.rst b/doc/board/starfive/pine64_star64.rst
new file mode 100644
index 00000000000..52e9a907917
--- /dev/null
+++ b/doc/board/starfive/pine64_star64.rst
@@ -0,0 +1,201 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+Pine64 Star64
+=============
+
+U-Boot for the Star64 uses the same U-Boot binaries as the VisionFive 2 board.
+In U-Boot SPL the actual board is detected and the device-tree patched
+accordingly.
+
+Building
+~~~~~~~~
+
+1. Add the RISC-V toolchain to your PATH.
+2. Setup ARCH & cross compilation environment variable:
+
+.. code-block:: none
+
+   export CROSS_COMPILE=<riscv64 toolchain prefix>
+
+The M-mode software OpenSBI provides the supervisor binary interface (SBI) and
+is responsible for the switch to S-Mode. It is a prerequisite to build U-Boot.
+Support for the JH7110 was introduced in OpenSBI 1.2. It is recommended to use
+a current release.
+
+.. code-block:: console
+
+	git clone https://github.com/riscv/opensbi.git
+	cd opensbi
+	make PLATFORM=generic FW_TEXT_START=0x40000000
+
+Now build the U-Boot SPL and U-Boot proper.
+
+.. code-block:: console
+
+	cd <U-Boot-dir>
+	make starfive_visionfive2_defconfig
+	make OPENSBI=$(opensbi_dir)/build/platform/generic/firmware/fw_dynamic.bin
+
+This will generate the U-Boot SPL image (spl/u-boot-spl.bin.normal.out) as well
+as the FIT image (u-boot.itb) with OpenSBI and U-Boot.
+
+Device-tree selection
+~~~~~~~~~~~~~~~~~~~~~
+
+U-Boot will set variable $fdtfile to starfive/jh7110-pine64-star64.dtb.
+
+To overrule this selection the variable can be set manually and saved in the
+environment
+
+::
+
+    env set fdtfile my_device-tree.dtb
+    env save
+
+or the configuration variable CONFIG_DEFAULT_FDT_FILE can be used to set to
+provide a default value.
+
+Boot source selection
+~~~~~~~~~~~~~~~~~~~~~
+
+Boot mode is selected by an MSEL-DIP marked S1804 and GPIO_0 position adjacent
+to the 40pin GPIO header. ON/ONKE and number markings of the MSEL-DIP are
+misleading; Instead refer to the ``L`` (0) and ``H`` (1) silkscreen for
+accurate selection.
+
++ (QSPI) Flash: 00
++ SD: 01
++ EMMC: 10
++ UART: 11
+
+Preparing the SD-Card
+~~~~~~~~~~~~~~~~~~~~~
+
+The device firmware loads U-Boot SPL (u-boot-spl.bin.normal.out) from the
+partition with type GUID 2E54B353-1271-4842-806F-E436D6AF6985. You are free
+to choose any partition number.
+
+With the default configuration U-Boot SPL loads the U-Boot FIT image
+(u-boot.itb) from partition 2 (CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION=0x2).
+When formatting it is recommended to use GUID
+BC13C2FF-59E6-4262-A352-B275FD6F7172 for this partition.
+
+The FIT image (u-boot.itb) is a combination of OpenSBI's fw_dynamic.bin,
+u-boot-nodtb.bin and the device tree blob.
+
+Format the SD card (make sure the disk has GPT, otherwise use gdisk to switch)
+
+.. code-block:: bash
+
+	sudo sgdisk --clear \
+	  --set-alignment=2 \
+	  --new=1:4096:8191 --change-name=1:spl --typecode=1:2E54B353-1271-4842-806F-E436D6AF6985\
+	  --new=2:8192:16383 --change-name=2:uboot --typecode=2:BC13C2FF-59E6-4262-A352-B275FD6F7172  \
+	  --new=3:16384:1654784 --change-name=3:system --typecode=3:EBD0A0A2-B9E5-4433-87C0-68B6B72699C7 \
+	  /dev/sdb
+
+Copy U-Boot to the SD card
+
+.. code-block:: bash
+
+	sudo dd if=u-boot-spl.bin.normal.out of=/dev/sdb1
+	sudo dd if=u-boot.itb of=/dev/sdb2
+
+	sudo mount /dev/sdb3 /mnt/
+	sudo cp u-boot-spl.bin.normal.out /mnt/
+	sudo cp u-boot.itb /mnt/
+	sudo cp Image.gz /mnt/
+	sudo cp initramfs.cpio.gz /mnt/
+	sudo cp jh7110-starfive-visionfive-2.dtb /mnt/
+	sudo umount /mnt
+
+Booting
+~~~~~~~
+
+Once you plugin the sdcard and power up, you should see the U-Boot prompt.
+
+Serial Number and MAC address issues
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+U-Boot requires valid EEPROM data to determine which board-specific fix-up to
+apply at runtime. This affects the size of memory initialized, network mac
+address numbering, and tuning of the network PHYs.
+
+The Star64 does not currently ship with unique serial numbers per-device.
+Devices follow a pattern where the last mac address bytes are a sum of 0x7558
+and the serial number (lower port mac0), or a sum of 0x7559 and the serial
+number (upper port mac1).
+
+As tested there are several 4gb model units where the serial number and network
+mac addresses collide with other devices (serial
+``STAR64V1-2310-D004E000-00000005``, MACs ``6c:cf:39:00:75:61``,
+``6c:cf:39:00:75:62``)
+
+Some early Star64 boards shipped with an uninitialized EEPROM and no write
+protect pull-up resistor in place. Later units of all 4gb and 8gb models
+sharing the same serial number in EEPROM data will have this problem that the
+network mac addresses are alike between different models and this may be
+corrected by defeating the write protect resistor to write new values. As an
+alternative to this, it may be worked around by overriding the mac addresses
+via U-Boot environment variables.
+
+It is required for any unit having uninitialized EEPROM and recommended for
+all later Star64 4gb model units (not properly serialized) to have decided on a
+new 6-byte serial number. This serial number should be high enough to
+avoid collision with other JH7110 boards and low enough not to overflow i.e.
+between ``cafe00`` and ``f00d00``.
+
+Update EEPROM values
+^^^^^^^^^^^^^^^^^^^^
+
+1. Prepare EEPROM data in memory
+
+::
+
+	## When there is no error to load existing data:
+	mac read_eeprom
+
+	## When there is an error to load non-existing data:
+	# "DRAM:  Not a StarFive EEPROM data format - magic error"
+	mac initialize
+
+2. Set Star64 values
+
+::
+
+	## Common values
+	mac vendor PINE64
+	mac pcb_revision c1
+	mac bom_revision A
+
+	## Device-specific values
+	# Year 2023 week 10 production date, 8GB DRAM, optional eMMC, serial cdef01
+	mac product_id STAR64V1-2310-D008E000-00cdef01
+
+	# Last three bytes mac0: 0x7558 + serial number 0xcdef01
+	mac mac0_address 6c:cf:39:ce:64:59
+
+	# Last three bytes mac1: 0x7559 + serial number 0xcdef01
+	mac mac1_address 6c:cf:39:ce:64:5a
+
+3. Defeat write-protect pull-up resistor (if installed) and write to EEPROM
+
+::
+
+	mac write_eeprom
+
+Set Variables in U-Boot
+^^^^^^^^^^^^^^^^^^^^^^^
+
+.. note:: Changing just the serial number will not alter your MAC address
+
+The MAC addresses may be "set" as follows by writing as a custom config to SPI
+(Change the last 3 bytes of MAC addreses as appropriate):
+
+::
+
+	env set serial# STAR64V1-2310-D008E000-00cdef01
+	env set ethaddr 6c:cf:39:ce:64:59
+	env set eth1addr 6c:cf:39:ce:64:5a
+	env save
+	reset
diff --git a/doc/develop/release_cycle.rst b/doc/develop/release_cycle.rst
index 383f4480c6e..c9fb07f59e1 100644
--- a/doc/develop/release_cycle.rst
+++ b/doc/develop/release_cycle.rst
@@ -73,7 +73,7 @@ For the next scheduled release, release candidates were made on::
 
 * U-Boot v2024.07-rc3 was released on Mon 20 May 2024.
 
-.. * U-Boot v2024.07-rc4 was released on Mon 03 June 2024.
+* U-Boot v2024.07-rc4 was released on Mon 03 June 2024.
 
 .. * U-Boot v2024.07-rc5 was released on Mon 17 June 2024.
 
diff --git a/doc/device-tree-bindings/clock/samsung,exynos850-clock.yaml b/doc/device-tree-bindings/clock/samsung,exynos850-clock.yaml
deleted file mode 100644
index a0906efe122..00000000000
--- a/doc/device-tree-bindings/clock/samsung,exynos850-clock.yaml
+++ /dev/null
@@ -1,307 +0,0 @@
-# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
-%YAML 1.2
----
-$id: http://devicetree.org/schemas/clock/samsung,exynos850-clock.yaml#
-$schema: http://devicetree.org/meta-schemas/core.yaml#
-
-title: Samsung Exynos850 SoC clock controller
-
-maintainers:
-  - Sam Protsenko <[email protected]>
-
-description: |
-  Exynos850 clock controller is comprised of several CMU units, generating
-  clocks for different domains. Those CMU units are modeled as separate device
-  tree nodes, and might depend on each other. Root clocks in that clock tree are
-  two external clocks:: OSCCLK (26 MHz) and RTCCLK (32768 Hz). Those external
-  clocks must be defined as fixed-rate clocks in dts.
-
-  CMU_TOP is a top-level CMU, where all base clocks are prepared using PLLs and
-  dividers; all other leaf clocks (other CMUs) are usually derived from CMU_TOP.
-
-  Each clock is assigned an identifier and client nodes can use this identifier
-  to specify the clock which they consume. All clocks available for usage
-  in clock consumer nodes are defined as preprocessor macros in
-  'dt-bindings/clock/exynos850.h' header.
-
-properties:
-  compatible:
-    enum:
-      - samsung,exynos850-cmu-top
-      - samsung,exynos850-cmu-apm
-      - samsung,exynos850-cmu-aud
-      - samsung,exynos850-cmu-cmgp
-      - samsung,exynos850-cmu-core
-      - samsung,exynos850-cmu-dpu
-      - samsung,exynos850-cmu-g3d
-      - samsung,exynos850-cmu-hsi
-      - samsung,exynos850-cmu-is
-      - samsung,exynos850-cmu-mfcmscl
-      - samsung,exynos850-cmu-peri
-
-  clocks:
-    minItems: 1
-    maxItems: 5
-
-  clock-names:
-    minItems: 1
-    maxItems: 5
-
-  "#clock-cells":
-    const: 1
-
-  reg:
-    maxItems: 1
-
-allOf:
-  - if:
-      properties:
-        compatible:
-          contains:
-            const: samsung,exynos850-cmu-top
-
-    then:
-      properties:
-        clocks:
-          items:
-            - description: External reference clock (26 MHz)
-
-        clock-names:
-          items:
-            - const: oscclk
-
-  - if:
-      properties:
-        compatible:
-          contains:
-            const: samsung,exynos850-cmu-apm
-
-    then:
-      properties:
-        clocks:
-          items:
-            - description: External reference clock (26 MHz)
-            - description: CMU_APM bus clock (from CMU_TOP)
-
-        clock-names:
-          items:
-            - const: oscclk
-            - const: dout_clkcmu_apm_bus
-
-  - if:
-      properties:
-        compatible:
-          contains:
-            const: samsung,exynos850-cmu-aud
-
-    then:
-      properties:
-        clocks:
-          items:
-            - description: External reference clock (26 MHz)
-            - description: AUD clock (from CMU_TOP)
-
-        clock-names:
-          items:
-            - const: oscclk
-            - const: dout_aud
-
-  - if:
-      properties:
-        compatible:
-          contains:
-            const: samsung,exynos850-cmu-cmgp
-
-    then:
-      properties:
-        clocks:
-          items:
-            - description: External reference clock (26 MHz)
-            - description: CMU_CMGP bus clock (from CMU_APM)
-
-        clock-names:
-          items:
-            - const: oscclk
-            - const: gout_clkcmu_cmgp_bus
-
-  - if:
-      properties:
-        compatible:
-          contains:
-            const: samsung,exynos850-cmu-core
-
-    then:
-      properties:
-        clocks:
-          items:
-            - description: External reference clock (26 MHz)
-            - description: CMU_CORE bus clock (from CMU_TOP)
-            - description: CCI clock (from CMU_TOP)
-            - description: eMMC clock (from CMU_TOP)
-            - description: SSS clock (from CMU_TOP)
-
-        clock-names:
-          items:
-            - const: oscclk
-            - const: dout_core_bus
-            - const: dout_core_cci
-            - const: dout_core_mmc_embd
-            - const: dout_core_sss
-
-  - if:
-      properties:
-        compatible:
-          contains:
-            const: samsung,exynos850-cmu-dpu
-
-    then:
-      properties:
-        clocks:
-          items:
-            - description: External reference clock (26 MHz)
-            - description: DPU clock (from CMU_TOP)
-
-        clock-names:
-          items:
-            - const: oscclk
-            - const: dout_dpu
-
-  - if:
-      properties:
-        compatible:
-          contains:
-            const: samsung,exynos850-cmu-g3d
-
-    then:
-      properties:
-        clocks:
-          items:
-            - description: External reference clock (26 MHz)
-            - description: G3D clock (from CMU_TOP)
-
-        clock-names:
-          items:
-            - const: oscclk
-            - const: dout_g3d_switch
-
-  - if:
-      properties:
-        compatible:
-          contains:
-            const: samsung,exynos850-cmu-hsi
-
-    then:
-      properties:
-        clocks:
-          items:
-            - description: External reference clock (26 MHz)
-            - description: External RTC clock (32768 Hz)
-            - description: CMU_HSI bus clock (from CMU_TOP)
-            - description: SD card clock (from CMU_TOP)
-            - description: USB 2.0 DRD clock (from CMU_TOP)
-
-        clock-names:
-          items:
-            - const: oscclk
-            - const: rtcclk
-            - const: dout_hsi_bus
-            - const: dout_hsi_mmc_card
-            - const: dout_hsi_usb20drd
-
-  - if:
-      properties:
-        compatible:
-          contains:
-            const: samsung,exynos850-cmu-is
-
-    then:
-      properties:
-        clocks:
-          items:
-            - description: External reference clock (26 MHz)
-            - description: CMU_IS bus clock (from CMU_TOP)
-            - description: Image Texture Processing core clock (from CMU_TOP)
-            - description: Visual Recognition Accelerator clock (from CMU_TOP)
-            - description: Geometric Distortion Correction clock (from CMU_TOP)
-
-        clock-names:
-          items:
-            - const: oscclk
-            - const: dout_is_bus
-            - const: dout_is_itp
-            - const: dout_is_vra
-            - const: dout_is_gdc
-
-  - if:
-      properties:
-        compatible:
-          contains:
-            const: samsung,exynos850-cmu-mfcmscl
-
-    then:
-      properties:
-        clocks:
-          items:
-            - description: External reference clock (26 MHz)
-            - description: Multi-Format Codec clock (from CMU_TOP)
-            - description: Memory to Memory Scaler clock (from CMU_TOP)
-            - description: Multi-Channel Scaler clock (from CMU_TOP)
-            - description: JPEG codec clock (from CMU_TOP)
-
-        clock-names:
-          items:
-            - const: oscclk
-            - const: dout_mfcmscl_mfc
-            - const: dout_mfcmscl_m2m
-            - const: dout_mfcmscl_mcsc
-            - const: dout_mfcmscl_jpeg
-
-  - if:
-      properties:
-        compatible:
-          contains:
-            const: samsung,exynos850-cmu-peri
-
-    then:
-      properties:
-        clocks:
-          items:
-            - description: External reference clock (26 MHz)
-            - description: CMU_PERI bus clock (from CMU_TOP)
-            - description: UART clock (from CMU_TOP)
-            - description: Parent clock for HSI2C and SPI (from CMU_TOP)
-
-        clock-names:
-          items:
-            - const: oscclk
-            - const: dout_peri_bus
-            - const: dout_peri_uart
-            - const: dout_peri_ip
-
-required:
-  - compatible
-  - "#clock-cells"
-  - clocks
-  - clock-names
-  - reg
-
-additionalProperties: false
-
-examples:
-  # Clock controller node for CMU_PERI
-  - |
-    #include <dt-bindings/clock/exynos850.h>
-
-    cmu_peri: clock-controller@10030000 {
-        compatible = "samsung,exynos850-cmu-peri";
-        reg = <0x10030000 0x8000>;
-        #clock-cells = <1>;
-
-        clocks = <&oscclk>, <&cmu_top CLK_DOUT_PERI_BUS>,
-                 <&cmu_top CLK_DOUT_PERI_UART>,
-                 <&cmu_top CLK_DOUT_PERI_IP>;
-        clock-names = "oscclk", "dout_peri_bus",
-                      "dout_peri_uart", "dout_peri_ip";
-    };
-
-...
diff --git a/doc/device-tree-bindings/soc/samsung/exynos-usi.yaml b/doc/device-tree-bindings/soc/samsung/exynos-usi.yaml
deleted file mode 100644
index 8e6423f1156..00000000000
--- a/doc/device-tree-bindings/soc/samsung/exynos-usi.yaml
+++ /dev/null
@@ -1,162 +0,0 @@
-# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
-%YAML 1.2
----
-$id: http://devicetree.org/schemas/soc/samsung/exynos-usi.yaml#
-$schema: http://devicetree.org/meta-schemas/core.yaml#
-
-title: Samsung's Exynos USI (Universal Serial Interface)
-
-maintainers:
-  - Sam Protsenko <[email protected]>
-
-description: |
-  USI IP-core provides selectable serial protocol (UART, SPI or High-Speed I2C).
-  USI shares almost all internal circuits within each protocol, so only one
-  protocol can be chosen at a time. USI is modeled as a node with zero or more
-  child nodes, each representing a serial sub-node device. The mode setting
-  selects which particular function will be used.
-
-properties:
-  $nodename:
-    pattern: "^usi@[0-9a-f]+$"
-
-  compatible:
-    enum:
-      - samsung,exynos850-usi
-
-  reg: true
-
-  clocks: true
-
-  clock-names: true
-
-  ranges: true
-
-  "#address-cells":
-    const: 1
-
-  "#size-cells":
-    const: 1
-
-  samsung,sysreg:
-    $ref: /schemas/types.yaml#/definitions/phandle-array
-    items:
-      - items:
-          - description: phandle to System Register syscon node
-          - description: offset of SW_CONF register for this USI controller
-    description:
-      Should be phandle/offset pair. The phandle to System Register syscon node
-      (for the same domain where this USI controller resides) and the offset
-      of SW_CONF register for this USI controller.
-
-  samsung,mode:
-    $ref: /schemas/types.yaml#/definitions/uint32
-    description:
-      Selects USI function (which serial protocol to use). Refer to
-      <include/dt-bindings/soc/samsung,exynos-usi.h> for valid USI mode values.
-
-  samsung,clkreq-on:
-    type: boolean
-    description:
-      Enable this property if underlying protocol requires the clock to be
-      continuously provided without automatic gating. As suggested by SoC
-      manual, it should be set in case of SPI/I2C slave, UART Rx and I2C
-      multi-master mode. Usually this property is needed if USI mode is set
-      to "UART".
-
-      This property is optional.
-
-patternProperties:
-  "^i2c@[0-9a-f]+$":
-    $ref: /schemas/i2c/i2c-exynos5.yaml
-    description: Child node describing underlying I2C
-
-  "^serial@[0-9a-f]+$":
-    $ref: /schemas/serial/samsung_uart.yaml
-    description: Child node describing underlying UART/serial
-
-  "^spi@[0-9a-f]+$":
-    $ref: /schemas/spi/samsung,spi.yaml
-    description: Child node describing underlying SPI
-
-required:
-  - compatible
-  - ranges
-  - "#address-cells"
-  - "#size-cells"
-  - samsung,sysreg
-  - samsung,mode
-
-if:
-  properties:
-    compatible:
-      contains:
-        enum:
-          - samsung,exynos850-usi
-
-then:
-  properties:
-    reg:
-      maxItems: 1
-
-    clocks:
-      items:
-        - description: Bus (APB) clock
-        - description: Operating clock for UART/SPI/I2C protocol
-
-    clock-names:
-      items:
-        - const: pclk
-        - const: ipclk
-
-  required:
-    - reg
-    - clocks
-    - clock-names
-
-else:
-  properties:
-    reg: false
-    clocks: false
-    clock-names: false
-    samsung,clkreq-on: false
-
-additionalProperties: false
-
-examples:
-  - |
-    #include <dt-bindings/interrupt-controller/arm-gic.h>
-    #include <dt-bindings/soc/samsung,exynos-usi.h>
-
-    usi0: usi@138200c0 {
-        compatible = "samsung,exynos850-usi";
-        reg = <0x138200c0 0x20>;
-        samsung,sysreg = <&sysreg_peri 0x1010>;
-        samsung,mode = <USI_V2_UART>;
-        samsung,clkreq-on; /* needed for UART mode */
-        #address-cells = <1>;
-        #size-cells = <1>;
-        ranges;
-        clocks = <&cmu_peri 32>, <&cmu_peri 31>;
-        clock-names = "pclk", "ipclk";
-
-        serial_0: serial@13820000 {
-            compatible = "samsung,exynos850-uart";
-            reg = <0x13820000 0xc0>;
-            interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
-            clocks = <&cmu_peri 32>, <&cmu_peri 31>;
-            clock-names = "uart", "clk_uart_baud0";
-            status = "disabled";
-        };
-
-        hsi2c_0: i2c@13820000 {
-            compatible = "samsung,exynosautov9-hsi2c";
-            reg = <0x13820000 0xc0>;
-            interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
-            #address-cells = <1>;
-            #size-cells = <0>;
-            clocks = <&cmu_peri 31>, <&cmu_peri 32>;
-            clock-names = "hsi2c", "hsi2c_pclk";
-            status = "disabled";
-        };
-    };