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| author | Tom Rini <[email protected]> | 2020-07-20 09:25:32 -0400 |
|---|---|---|
| committer | Tom Rini <[email protected]> | 2020-07-20 09:25:32 -0400 |
| commit | 7303ba10a4a39852b9ba356fae5656b43122eec6 (patch) | |
| tree | 4546d038f3daf513996fa0590f83274c01c3c501 /doc | |
| parent | 49cf75101db58ad3540d8de6749cf0c1d780dc76 (diff) | |
| parent | 2a3d9a7af9b3f7abad4d1bc4d40f1d665a54da8f (diff) | |
Merge https://gitlab.denx.de/u-boot/custodians/u-boot-x86
- dm: core: Don't show an ACPI warning if there is no ordering
- x86: Enhance MTRR functionality to support multiple CPUs
Diffstat (limited to 'doc')
| -rw-r--r-- | doc/board/google/chromebook_coral.rst | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/doc/board/google/chromebook_coral.rst b/doc/board/google/chromebook_coral.rst index 40bd9397d42..c39f1e310c7 100644 --- a/doc/board/google/chromebook_coral.rst +++ b/doc/board/google/chromebook_coral.rst @@ -188,6 +188,7 @@ Partial memory map fef00000 1000 CONFIG_BOOTSTAGE_STASH_ADDR fef00000 Base of CAR region + 30000 AP_DEFAULT_BASE (used to start up additional CPUs) f0000 CONFIG_ROM_TABLE_ADDR 120000 BSS (defined in u-boot-spl.lds) 200000 FSP-S (which is run after U-Boot is relocated) |