Merge branch '2022-06-06-finish-SPL-Kconfig-migration' into next

- Bring in a number of series of patches that migrate all remaining
  CONFIG_SPL symbols to Kconfig, remove some dead code that this
  uncovered and then start to tighten the dependencies in Kconfig now
  that everything is migrated and these relationships can be clearly
  expressed.

3 files changed, 55 insertions, 1 deletions

diff --git a/doc/develop/driver-model/design.rst b/doc/develop/driver-model/design.rst
index 5f33f9fbb32..a75d637ec33 100644
--- a/doc/develop/driver-model/design.rst
+++ b/doc/develop/driver-model/design.rst
@@ -1135,7 +1135,7 @@ constrained systems.
 To enable driver model in SPL, define CONFIG_SPL_DM. You might want to
 consider the following option also. See the main README for more details.
 
-   - CONFIG_SYS_MALLOC_SIMPLE
+   - CONFIG_SPL_SYS_MALLOC_SIMPLE
    - CONFIG_DM_WARN
    - CONFIG_DM_DEVICE_REMOVE
    - CONFIG_DM_STDIO
diff --git a/doc/imx/common/imx6.txt b/doc/imx/common/imx6.txt
index 9007cfbf587..c5554d8d6b3 100644
--- a/doc/imx/common/imx6.txt
+++ b/doc/imx/common/imx6.txt
@@ -162,3 +162,34 @@ icorem6qdl> nand write ${loadaddr} uboot ${filesize}
 NAND write: device 0 offset 0x200000, size 0x8fd26
  589094 bytes written: OK
 icorem6qdl>
+
+SPL Stack size and location notes
+---------------------------------
+
+If we have CONFIG_MX6_OCRAM_256KB then see Figure 8.4.1 in IMX6DQ Reference
+manuals:
+  - IMX6DQ OCRAM (IRAM) is from 0x00907000 to 0x0093FFFF
+  - BOOT ROM stack is at 0x0093FFB8
+  - if icache/dcache is enabled (eFuse/strapping controlled) then the
+    IMX BOOT ROM will setup MMU table at 0x00938000, therefore we need to
+    fit between 0x00907000 and 0x00938000.
+  - Additionally the BOOT ROM loads what they consider the firmware image
+    which consists of a 4K header in front of us that contains the IVT, DCD
+    and some padding thus 'our' max size is really 0x00908000 - 0x00938000
+    or 192KB
+  - Pad SPL to 196KB (4KB header + 192KB max size). This allows to write the
+    SPL/U-Boot combination generated with u-boot-with-spl.imx directly to a
+    boot media (given that boot media specific offset is configured properly).
+and if we don't, see Figure 8-3 in IMX6SDL Reference manuals:
+  - IMX6SDL OCRAM (IRAM) is from 0x00907000 to 0x0091FFFF
+  - BOOT ROM stack is at 0x0091FFB8
+  - if icache/dcache is enabled (eFuse/strapping controlled) then the
+    IMX BOOT ROM will setup MMU table at 0x00918000, therefore we need to
+    fit between 0x00907000 and 0x00918000.
+  - Additionally the BOOT ROM loads what they consider the firmware image
+    which consists of a 4K header in front of us that contains the IVT, DCD
+    and some padding thus 'our' max size is really 0x00908000 - 0x00918000
+    or 64KB
+  - Pad SPL to 68KB (4KB header + 64KB max size). This allows to write the
+    SPL/U-Boot combination generated with u-boot-with-spl.imx directly to a
+    boot media (given that boot media specific offset is configured properly).
diff --git a/doc/imx/common/imx7.txt b/doc/imx/common/imx7.txt
new file mode 100644
index 00000000000..b9db10341ad
--- /dev/null
+++ b/doc/imx/common/imx7.txt
@@ -0,0 +1,23 @@
+U-Boot for Freescale i.MX7
+
+SPL Stack size and location notes
+---------------------------------
+See figure 6-22 in i.MX 7Dual/Solo Reference manuals:
+  - IMX7D/S OCRAM free area RAM (OCRAM) is from 0x00910000 to
+    0x00946C00.
+  - Set the stack at the end of the free area section, at 0x00946BB8.
+  - The BOOT ROM loads what they consider the firmware image
+    which consists of a 4K header in front of us that contains the IVT, DCD
+    and some padding. However, the manual also states that the ROM uses the
+    OCRAM_EPCD and OCRAM_PXP areas for itself. While the SPL is free to use
+    this range for stack and malloc, the SPL itself must fit below 0x920000,
+    or the image will be truncated in at least some boot modes like USB SDP.
+    Thus our max size is really 0x00920000 - 0x00912000. If necessary,
+    CONFIG_SPL_TEXT_BASE could be moved to 0x00911000 to gain 4KB of space
+    for the SPL, but 56KB should be more than enough for the SPL.
+  - Pad SPL to 68KB (4KB header + 56KB max size + 8KB extra padding)
+    The extra padding could be removed, but this value was used historically
+    based on an incorrect CONFIG_SPL_MAX_SIZE definition.
+    This allows to write the SPL/U-Boot combination generated with
+    u-boot-with-spl.imx directly to a boot media (given that boot media specific
+    offset is configured properly).