Merge branch 'next' of https://source.denx.de/u-boot/custodians/u-boot-riscv into next

CI result shows no issue:
https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/22315
----------------------------------------------------------------
- Aspeed: Add AST2700 board (Ibex RISC-V core) support
        - Add timer, dram controller, network support
- Sophgo: Add clock controller support for Milk-V Duo

3 files changed, 36 insertions, 0 deletions

diff --git a/doc/board/aspeed/ibex-ast2700.rst b/doc/board/aspeed/ibex-ast2700.rst
new file mode 100644
index 00000000000..511bd081ba2
--- /dev/null
+++ b/doc/board/aspeed/ibex-ast2700.rst
@@ -0,0 +1,26 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+IBex AST2700
+============
+
+AST2700 integrates an IBex RISC-V 32-bits CPU as the boot MCU to execute the
+first stage bootlaoder, namely SPL.
+
+Build
+-----
+
+1. Prepare the toolchains and make sure the $PATH to toolchains is correct.
+2. Use `make ibex-ast2700_defconfig` in u-boot root to build the image
+
+Running U-Boot SPL
+------------------
+
+The U-Boot SPL will boot in M mode and load the FIT image which includes
+the 2nd stage bootloaders executed by the main processor Cortex-A35.
+
+
+Burn U-Boot to SPI Flash
+------------------------
+
+Use SPI flash programmer (e.g. SF100) to program the u-book-spl.bin with the
+offset 0x80 bytes to the SPI flash beginning.
diff --git a/doc/board/aspeed/index.rst b/doc/board/aspeed/index.rst
new file mode 100644
index 00000000000..d784c88494f
--- /dev/null
+++ b/doc/board/aspeed/index.rst
@@ -0,0 +1,9 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+Aspeed
+======
+
+.. toctree::
+   :maxdepth: 2
+
+   ibex-ast2700
diff --git a/doc/board/index.rst b/doc/board/index.rst
index 417c128c7af..3fb7c84f10c 100644
--- a/doc/board/index.rst
+++ b/doc/board/index.rst
@@ -14,6 +14,7 @@ Board-specific doc
    anbernic/index
    apple/index
    armltd/index
+   aspeed/index
    asus/index
    atmel/index
    beacon/index