diff options
| author | Bin Meng <[email protected]> | 2016-02-17 00:16:25 -0800 |
|---|---|---|
| committer | Bin Meng <[email protected]> | 2016-02-21 13:42:52 +0800 |
| commit | a2e3b05e16c96ccc5929d60457938cd96912d758 (patch) | |
| tree | 507b98f4bdf64a0130bee108d6e9aff15b62dddd /doc | |
| parent | 87077e97d1a72286871d03a6f06903245b9caacd (diff) | |
x86: Add Intel Cougar Canyon 2 board
This adds basic support to Intel Cougar Canyon 2 board, a board
based on Chief River platform with an Ivy Bridge processor and
a Panther Point chipset.
Signed-off-by: Bin Meng <[email protected]>
Acked-by: Simon Glass <[email protected]>
Diffstat (limited to 'doc')
| -rw-r--r-- | doc/README.x86 | 21 |
1 files changed, 21 insertions, 0 deletions
diff --git a/doc/README.x86 b/doc/README.x86 index 6d9cb10edc8..948decac493 100644 --- a/doc/README.x86 +++ b/doc/README.x86 @@ -133,6 +133,27 @@ $ make all --- +Intel Cougar Canyon 2 specific instructions for bare mode: + +This uses Intel FSP for 3rd generation Intel Core and Intel Celeron processors +with mobile Intel HM76 and QM77 chipsets platform. Download it from Intel FSP +website and put the .fd file (CHIEFRIVER_FSP_GOLD_001_09-OCTOBER-2013.fd at the +time of writing) in the board directory and rename it to fsp.bin. + +Now build U-Boot and obtain u-boot.rom + +$ make cougarcanyon2_defconfig +$ make all + +The board has two 8MB SPI flashes mounted, which are called SPI-0 and SPI-1 in +the board manual. The SPI-0 flash should have flash descriptor plus ME firmware +and SPI-1 flash is used to store U-Boot. For convenience, the complete 8MB SPI-0 +flash image is included in the FSP package (named Rom00_8M_MB_PPT.bin). Program +this image to the SPI-0 flash according to the board manual just once and we are +all set. For programming U-Boot we just need to program SPI-1 flash. + +--- + Intel Minnowboard Max instructions for bare mode: This uses as FSP as with Crown Bay, except it is for the Atom E3800 series. |