Merge branch '2022-12-05-Kconfig-migrations-and-renames' into next

- First batch of the patches that end up with
  scripts/config_whitelist.tx being empty. Mostly migrations and a
  little bit of code removal and CFG renaming.

23 files changed, 64 insertions, 80 deletions

diff --git a/doc/README.POST b/doc/README.POST
index 1d1c25bdf9e..5d92f3fe6e9 100644
--- a/doc/README.POST
+++ b/doc/README.POST
@@ -242,11 +242,11 @@ storage server and etc.
 
 All POST-related code will be #ifdef'ed with the CONFIG_POST macro.
 This macro will be defined in the config_<board>.h file for those
-boards that need POST. The CONFIG_POST macro will contain the list of
+boards that need POST. The CFG_POST macro will contain the list of
 POST tests for the board. The macro will have the format of array
 composed of post_test structures:
 
-#define CONFIG_POST \
+#define CFG_POST \
 	{
 		"On-board peripherals test", "board", \
 		"  This test performs full check-up of the " \
@@ -257,7 +257,7 @@ composed of post_test structures:
 
 A new file, post.h, will be created in the include/ directory. This
 file will contain common POST declarations and will define a set of
-macros that will be reused for defining CONFIG_POST. As an example,
+macros that will be reused for defining CFG_POST. As an example,
 the following macro may be defined:
 
 #define POST_CACHE \
diff --git a/doc/README.arm-relocation b/doc/README.arm-relocation
index 6bb4e178474..69882a76a36 100644
--- a/doc/README.arm-relocation
+++ b/doc/README.arm-relocation
@@ -53,8 +53,8 @@ c) end executes this code
 d) this initialize CPU, RAM, ... and copy itself to RAM
    (this bin must fit in one page, so board_init_f()
     don;t fit in it ... )
-e) there it copy u-boot to CONFIG_SYS_NAND_U_BOOT_DST and
-   starts this image @ CONFIG_SYS_NAND_U_BOOT_START
+e) there it copy u-boot to CFG_SYS_NAND_U_BOOT_DST and
+   starts this image @ CFG_SYS_NAND_U_BOOT_START
 f) u-boot code steps through board_init_f() and calculates
    the relocation address and copy itself to it
 
@@ -86,8 +86,8 @@ Relocation with SPL (example for the tx25 booting from NAND Flash):
 
 - The First page contains u-boot code from drivers/mtd/nand/raw/mxc_nand_spl.c
   which inits the dram, cpu registers, reloacte itself to CONFIG_SPL_TEXT_BASE	and loads
-  the "real" u-boot to CONFIG_SYS_NAND_U_BOOT_DST and starts execution
-  @CONFIG_SYS_NAND_U_BOOT_START
+  the "real" u-boot to CFG_SYS_NAND_U_BOOT_DST and starts execution
+  @CFG_SYS_NAND_U_BOOT_START
 
 - This u-boot does no RAM init, nor CPU register setup. Just look
   where it has to copy and relocate itself to this address. If
diff --git a/doc/README.atmel_mci b/doc/README.atmel_mci
index 00e64ba0c7d..0b6d2c53db7 100644
--- a/doc/README.atmel_mci
+++ b/doc/README.atmel_mci
@@ -60,7 +60,7 @@ int board_mmc_init(struct bd_info *bd)
 /* this is a weak define that we are overriding */
 int board_mmc_getcd(struct mmc *mmc)
 {
-	return !at91_get_gpio_value(CONFIG_SYS_MMC_CD_PIN);
+	return !at91_get_gpio_value(CFG_SYS_MMC_CD_PIN);
 }
 
 #endif
@@ -70,5 +70,5 @@ and the board definition files needs:
 /* SD/MMC card */
 #define CONFIG_GENERIC_ATMEL_MCI	1
 #define CONFIG_ATMEL_MCI_PORTB		1	/* Atmel XE-EK uses port B */
-#define CONFIG_SYS_MMC_CD_PIN		AT91_PIN_PC9
+#define CFG_SYS_MMC_CD_PIN		AT91_PIN_PC9
 #define CONFIG_CMD_MMC			1
diff --git a/doc/README.cfi b/doc/README.cfi
index ad52850818f..38185747028 100644
--- a/doc/README.cfi
+++ b/doc/README.cfi
@@ -35,12 +35,12 @@ In addition, the t3corp board defines the routine thusly:
 void flash_cmd_reset(flash_info_t *info)
 {
 	/*
-	 * FLASH at address CONFIG_SYS_FLASH_BASE is a Spansion chip and
+	 * FLASH at address CFG_SYS_FLASH_BASE is a Spansion chip and
 	 * needs the Spansion type reset commands. The other flash chip
 	 * is located behind a FPGA (Xilinx DS617) and needs the Intel type
 	 * reset command.
 	 */
-	if (info->start[0] == CONFIG_SYS_FLASH_BASE)
+	if (info->start[0] == CFG_SYS_FLASH_BASE)
 		flash_write_cmd(info, 0, 0, AMD_CMD_RESET);
 	else
 		flash_write_cmd(info, 0, 0, FLASH_CMD_RESET);
diff --git a/doc/README.davinci b/doc/README.davinci
index 607531af2a8..326efa0a2d6 100644
--- a/doc/README.davinci
+++ b/doc/README.davinci
@@ -75,7 +75,7 @@ http://www.ti.com/tool/TMDXLCDK138
 Davinci special defines
 =======================
 
-CONFIG_SYS_DV_NOR_BOOT_CFG:	AM18xx based boards, booting in NOR Boot mode
+CFG_SYS_DV_NOR_BOOT_CFG:	AM18xx based boards, booting in NOR Boot mode
 				need a "NOR Boot Configuration Word" stored
 				in the NOR Flash. This define adds this.
 				More Info about this, see:
diff --git a/doc/README.fsl-ddr b/doc/README.fsl-ddr
index cec5d94df4a..10e63f3be1d 100644
--- a/doc/README.fsl-ddr
+++ b/doc/README.fsl-ddr
@@ -137,7 +137,7 @@ Memory testing options for mpc85xx
 2. Memory test can be done with Power-On-Self-Test function, activated at
    compile time.
 
-   In order to enable the POST memory test, CONFIG_POST needs to be
+   In order to enable the POST memory test, CFG_POST needs to be
    defined in board configuraiton header file. By default, POST memory test
    performs a fast test. A slow test can be enabled by changing the flag at
    compiling time. To test memory bigger than 2GB, 36BIT support is needed.
diff --git a/doc/README.fsl_iim b/doc/README.fsl_iim
index e087f5e0e4f..78d3cb8b3ef 100644
--- a/doc/README.fsl_iim
+++ b/doc/README.fsl_iim
@@ -45,4 +45,4 @@ Fuse operations:
 Configuration:
 
    CONFIG_FSL_IIM
-      Define this to enable the fsl_iim driver.
+      Enable this to enable the fsl_iim driver.
diff --git a/doc/README.generic_usb_ohci b/doc/README.generic_usb_ohci
index 82fea6201d6..767614cbc6d 100644
--- a/doc/README.generic_usb_ohci
+++ b/doc/README.generic_usb_ohci
@@ -11,7 +11,7 @@ Configuration options
 
 	CONFIG_USB_OHCI_NEW: enable the new OHCI driver
 
-	CONFIG_SYS_USB_OHCI_REGS_BASE: defines the base address of the OHCI
+	CFG_SYS_USB_OHCI_REGS_BASE: defines the base address of the OHCI
 				registers
 
 	CONFIG_SYS_USB_OHCI_SLOT_NAME: slot name
diff --git a/doc/README.hwconfig b/doc/README.hwconfig
index b6ddb438cfa..5408a22bb6a 100644
--- a/doc/README.hwconfig
+++ b/doc/README.hwconfig
@@ -1,6 +1,3 @@
-To enable this feature just define CONFIG_HWCONFIG in your board
-config file.
-
 This implements a simple hwconfig infrastructure: an
 interface for software knobs to control hardware.
 
diff --git a/doc/README.mpc85xx b/doc/README.mpc85xx
index 3c6ebbdb0e6..bafffe6dc51 100644
--- a/doc/README.mpc85xx
+++ b/doc/README.mpc85xx
@@ -59,13 +59,13 @@ A) defined(CONFIG_SYS_RAMBOOT) i.e. SD, SPI, NAND RAMBOOT & NAND_SPL boot
    3) TLB entry for the stack during AS1
        Location	  : Lable "create_init_ram_area"
        TLB Entry  : 14
-       EPN -->RPN : CONFIG_SYS_INIT_RAM_ADDR --> CONFIG_SYS_INIT_RAM_ADDR
+       EPN -->RPN : CFG_SYS_INIT_RAM_ADDR --> CFG_SYS_INIT_RAM_ADDR
        Properties : 16K, AS1, IPROT
 
    4) TLB entry for CCSRBAR during AS1 execution
        Location	  : cpu_init_early_f
        TLB Entry  : 13
-       EPN -->RPN : CONFIG_SYS_CCSRBAR --> CONFIG_SYS_CCSRBAR
+       EPN -->RPN : CFG_SYS_CCSRBAR --> CFG_SYS_CCSRBAR
        Properties : 1M, AS1, I, G
 
    5) Invalidate unproctected TLB Entries
@@ -84,7 +84,7 @@ A) defined(CONFIG_SYS_RAMBOOT) i.e. SD, SPI, NAND RAMBOOT & NAND_SPL boot
    8) Update Flash's TLB entry
        Location	  : Board_init_r
        TLB entry  : Search from TLB entries
-       EPN -->RPN : CONFIG_SYS_FLASH_BASE --> CONFIG_SYS_FLASH_BASE_PHYS
+       EPN -->RPN : CFG_SYS_FLASH_BASE --> CFG_SYS_FLASH_BASE_PHYS
        Properties : Board specific size, AS0, I, G, IPROT
 
 
@@ -94,7 +94,7 @@ B) !defined(CONFIG_SYS_RAMBOOT) i.e. NOR boot
        Location	  : Label "_start"
        TLB Entry  : CONFIG_SYS_PPC_E500_DEBUG_TLB
 #if defined(CONFIG_NXP_ESBC)
-       EPN -->RPN : CONFIG_SYS_MONITOR_BASE --> CONFIG_SYS_PBI_FLASH_WINDOW
+       EPN -->RPN : CONFIG_SYS_MONITOR_BASE --> CFG_SYS_PBI_FLASH_WINDOW
        Properties : 1M, AS1, I, G, IPROT
 #else
        EPN -->RPN : CONFIG_SYS_MONITOR_BASE & 0xffc00000 --> 0xffc00000
@@ -105,7 +105,7 @@ B) !defined(CONFIG_SYS_RAMBOOT) i.e. NOR boot
        Location	  : Label "create_init_ram_area"
        TLB Entry  : 15
 #if defined(CONFIG_NXP_ESBC)
-       EPN -->RPN : CONFIG_SYS_MONITOR_BASE --> CONFIG_SYS_PBI_FLASH_WINDOW
+       EPN -->RPN : CONFIG_SYS_MONITOR_BASE --> CFG_SYS_PBI_FLASH_WINDOW
        Properties : 1M, AS1, I, G, IPROT
 #else
        EPN -->RPN : CONFIG_SYS_MONITOR_BASE & 0xffc00000 --> 0xffc00000
@@ -115,13 +115,13 @@ B) !defined(CONFIG_SYS_RAMBOOT) i.e. NOR boot
    3) TLB entry for the stack during AS1
        Location	  : Lable "create_init_ram_area"
        TLB Entry  : 14
-       EPN -->RPN : CONFIG_SYS_INIT_RAM_ADDR --> CONFIG_SYS_INIT_RAM_ADDR
+       EPN -->RPN : CFG_SYS_INIT_RAM_ADDR --> CFG_SYS_INIT_RAM_ADDR
        Properties : 16K, AS1, IPROT
 
    4) TLB entry for CCSRBAR during AS1 execution
        Location	  : cpu_init_early_f
        TLB Entry  : 13
-       EPN -->RPN : CONFIG_SYS_CCSRBAR --> CONFIG_SYS_CCSRBAR
+       EPN -->RPN : CFG_SYS_CCSRBAR --> CFG_SYS_CCSRBAR
        Properties : 1M, AS1, I, G
 
    5) TLB entry for Errata workaround CONFIG_SYS_FSL_ERRATUM_IFC_A003399
@@ -162,5 +162,5 @@ B) !defined(CONFIG_SYS_RAMBOOT) i.e. NOR boot
    12) Update Flash's TLB entry
        Location	  : Board_init_r
        TLB entry  : Search from TLB entries
-       EPN -->RPN : CONFIG_SYS_FLASH_BASE --> CONFIG_SYS_FLASH_BASE_PHYS
+       EPN -->RPN : CFG_SYS_FLASH_BASE --> CFG_SYS_FLASH_BASE_PHYS
        Properties : Board specific size, AS0, I, G, IPROT
diff --git a/doc/README.nand b/doc/README.nand
index d1ce30768b9..37657512533 100644
--- a/doc/README.nand
+++ b/doc/README.nand
@@ -99,16 +99,6 @@ Configuration Options:
    CONFIG_CMD_NAND_TORTURE
       Enables the torture command (see description of this command below).
 
-   CONFIG_SYS_NAND_MAX_ECCPOS
-      If specified, overrides the maximum number of ECC bytes
-      supported.  Useful for reducing image size, especially with SPL.
-      This must be at least 48 if nand_base.c is used.
-
-   CONFIG_SYS_NAND_MAX_OOBFREE
-      If specified, overrides the maximum number of free OOB regions
-      supported.  Useful for reducing image size, especially with SPL.
-      This must be at least 2 if nand_base.c is used.
-
    CONFIG_SYS_NAND_MAX_CHIPS
       The maximum number of NAND chips per device to be supported.
 
@@ -144,7 +134,7 @@ Configuration Options:
 	chip.IO_ADDR_R = ...;
 	chip.IO_ADDR_W = ...;
 
-	if (nand_scan_ident(mtd, CONFIG_SYS_MAX_NAND_CHIPS, NULL))
+	if (nand_scan_ident(mtd, CFG_SYS_MAX_NAND_CHIPS, NULL))
 		error out
 
 	/*
diff --git a/doc/README.omap3 b/doc/README.omap3
index 208714ad658..3a1ac8101d6 100644
--- a/doc/README.omap3
+++ b/doc/README.omap3
@@ -146,11 +146,11 @@ implementation for OMAP3 works for you so the u-boot version should also.
 When you require the SPL to read with BCH8 there are two more configs to
 change:
 
- * CONFIG_SYS_NAND_ECCPOS (must be the same as .eccpos in
+ * CFG_SYS_NAND_ECCPOS (must be the same as .eccpos in
    GPMC_NAND_HW_BCH8_ECC_LAYOUT defined in
    arch/arm/include/asm/arch-omap3/omap_gpmc.h)
- * CONFIG_SYS_NAND_ECCSIZE must be 512
- * CONFIG_SYS_NAND_ECCBYTES must be 13 for this BCH8 setup
+ * CFG_SYS_NAND_ECCSIZE must be 512
+ * CFG_SYS_NAND_ECCBYTES must be 13 for this BCH8 setup
 
 Acknowledgements
 ================
diff --git a/doc/README.serial_multi b/doc/README.serial_multi
index c9049fd01d6..0446fe95937 100644
--- a/doc/README.serial_multi
+++ b/doc/README.serial_multi
@@ -35,7 +35,7 @@ just after switching the console:
 	setenv sout serial_scc; setenv baudrate 38400
 
 After that press 'enter' at the SCC console. Note that baudrates <38400
-are not allowed on LWMON with watchdog enabled (see CONFIG_SYS_BAUDRATE_TABLE in
+are not allowed on LWMON with watchdog enabled (see CFG_SYS_BAUDRATE_TABLE in
 include/configs/lwmon.h).
 
 
diff --git a/doc/arch/m68k.rst b/doc/arch/m68k.rst
index 15806dfaee1..770327fea21 100644
--- a/doc/arch/m68k.rst
+++ b/doc/arch/m68k.rst
@@ -112,16 +112,16 @@ CONFIG_M5272:
 Other options, generally set inside include/configs/<boardname>.h, they may
 apply to one or more cpu for the ColdFire family:
 
-CONFIG_SYS_MBAR:
+CFG_SYS_MBAR:
   defines the base address of the MCF5272 configuration registers
-CONFIG_SYS_SCR:
+CFG_SYS_SCR:
   defines the contents of the System Configuration Register
-CONFIG_SYS_SPR:
+CFG_SYS_SPR:
   defines the contents of the System Protection Register
-CONFIG_SYS_MFD:
+CFG_SYS_MFD:
   defines the PLL Multiplication Factor Divider
   (see table 9-4 of MCF user manual)
-CONFIG_SYS_RFD:
+CFG_SYS_RFD:
   defines the PLL Reduce Frequency Devider
   (see table 9-4 of MCF user manual)
 CONFIG_SYS_CSx_BASE:
@@ -136,33 +136,33 @@ CONFIG_SYS_CSx_RO:
   if set to 0 chip select x is read/write else chip select is read only
 CONFIG_SYS_CSx_WS:
   defines the number of wait states  of chip select x
-CONFIG_SYS_CACHE_ICACR:
+CFG_SYS_CACHE_ICACR:
   cache-related registers config
-CONFIG_SYS_CACHE_DCACR:
+CFG_SYS_CACHE_DCACR:
   cache-related registers config
 CONFIG_SYS_CACHE_ACRX:
   cache-related registers config
-CONFIG_SYS_SDRAM_BASE:
+CFG_SYS_SDRAM_BASE:
   SDRAM config for SDRAM controller-specific registers
-CONFIG_SYS_SDRAM_SIZE:
+CFG_SYS_SDRAM_SIZE:
   SDRAM config for SDRAM controller-specific registers
-CONFIG_SYS_SDRAM_BASEX:
+CFG_SYS_SDRAM_BASEX:
   SDRAM config for SDRAM controller-specific registers
-CONFIG_SYS_SDRAM_CFG1:
+CFG_SYS_SDRAM_CFG1:
   SDRAM config for SDRAM controller-specific registers
-CONFIG_SYS_SDRAM_CFG2:
+CFG_SYS_SDRAM_CFG2:
   SDRAM config for SDRAM controller-specific registers
-CONFIG_SYS_SDRAM_CTRL:
+CFG_SYS_SDRAM_CTRL:
   SDRAM config for SDRAM controller-specific registers
-CONFIG_SYS_SDRAM_MODE:
+CFG_SYS_SDRAM_MODE:
   SDRAM config for SDRAM controller-specific registers
-CONFIG_SYS_SDRAM_EMOD:
+CFG_SYS_SDRAM_EMOD:
   SDRAM config for SDRAM controller-specific registers, please
   see arch/m68k/cpu/<specific_cpu>/start.S files to see how
   these options are used.
 CONFIG_MCFUART:
   defines enabling of ColdFire UART driver
-CONFIG_SYS_UART_PORT:
+CFG_SYS_UART_PORT:
   defines the UART port to be used (only a single UART can be actually enabled)
-CONFIG_SYS_SBFHDR_SIZE:
+CFG_SYS_SBFHDR_SIZE:
   size of the prepended SBF header, if any
diff --git a/doc/arch/nios2.rst b/doc/arch/nios2.rst
index 35defb0af0b..34a75e7fb00 100644
--- a/doc/arch/nios2.rst
+++ b/doc/arch/nios2.rst
@@ -96,8 +96,8 @@ to 0xDxxx_xxxx.
 
 .. code-block:: c
 
-   #define CONFIG_SYS_SDRAM_BASE		0xc8000000
-   #define CONFIG_SYS_SDRAM_SIZE		0x08000000
+   #define CFG_SYS_SDRAM_BASE		0xc8000000
+   #define CFG_SYS_SDRAM_SIZE		0x08000000
 
 You will need to change the environment variables location and setting,
 too. You may change other configs to fit your board.
diff --git a/doc/arch/sandbox/sandbox.rst b/doc/arch/sandbox/sandbox.rst
index 34c4e06d9b8..e6d84036516 100644
--- a/doc/arch/sandbox/sandbox.rst
+++ b/doc/arch/sandbox/sandbox.rst
@@ -56,11 +56,8 @@ To run sandbox U-Boot use something like::
 
 Note: If you get errors about 'sdl-config: Command not found' you may need to
 install libsdl2.0-dev or similar to get SDL support. Alternatively you can
-build sandbox without SDL (i.e. no display/keyboard support) by removing
-the CONFIG_SANDBOX_SDL line in include/configs/sandbox.h or using::
-
-   make sandbox_defconfig all NO_SDL=1
-   ./u-boot
+build sandbox without SDL (i.e. no display/keyboard support) by disabling
+CONFIG_SANDBOX_SDL in the .config file.
 
 U-Boot will start on your computer, showing a sandbox emulation of the serial
 console::
@@ -84,7 +81,7 @@ To exit, type 'poweroff' or press Ctrl-C.
 Console / LCD support
 ---------------------
 
-Assuming that CONFIG_SANDBOX_SDL is defined when building, you can run the
+Assuming that CONFIG_SANDBOX_SDL is enabled when building, you can run the
 sandbox with LCD and keyboard emulation, using something like::
 
    ./u-boot -d u-boot.dtb -l
diff --git a/doc/board/ti/am335x_evm.rst b/doc/board/ti/am335x_evm.rst
index a90f32da7ae..0b230cf7c75 100644
--- a/doc/board/ti/am335x_evm.rst
+++ b/doc/board/ti/am335x_evm.rst
@@ -54,7 +54,7 @@ Step-1: Building u-boot for NAND boot
 	CONFIG_SYS_NAND_PAGE_SIZE	number of main bytes in NAND page
 	CONFIG_SYS_NAND_OOBSIZE		number of OOB bytes in NAND page
 	CONFIG_SYS_NAND_BLOCK_SIZE	number of bytes in NAND erase-block
-	CONFIG_SYS_NAND_ECCPOS		ECC map for NAND page
+	CFG_SYS_NAND_ECCPOS		ECC map for NAND page
 	CONFIG_NAND_OMAP_ECCSCHEME	(refer doc/README.nand)
 
 Step-2: Flashing NAND via MMC/SD
diff --git a/doc/build/tools.rst b/doc/build/tools.rst
index c06f9152741..ec017229258 100644
--- a/doc/build/tools.rst
+++ b/doc/build/tools.rst
@@ -44,4 +44,4 @@ applications using a linux toolchain (gcc, bash, etc), targeting respectively
 Launch the MSYS2 shell of the MSYS2 environment, and do the following::
 
    $ make tools-only_defconfig
-   $ make tools-only NO_SDL=1
+   $ make tools-only
diff --git a/doc/develop/driver-model/migration.rst b/doc/develop/driver-model/migration.rst
index 43665de64f5..fe1ae210def 100644
--- a/doc/develop/driver-model/migration.rst
+++ b/doc/develop/driver-model/migration.rst
@@ -99,7 +99,7 @@ The I2C subsystem has supported the driver model since early 2015.
 Maintainers should submit patches switching over to using CONFIG_DM_I2C and
 other base driver model options in time for inclusion in the 2021.10 release.
 
-CONFIG_SYS_TIMER_RATE and CONFIG_SYS_TIMER_COUNTER
+CFG_SYS_TIMER_RATE and CFG_SYS_TIMER_COUNTER
 --------------------------------------------------
 Deadline: 2023.01
 
diff --git a/doc/device-tree-bindings/video/exynos-dp.txt b/doc/device-tree-bindings/video/exynos-dp.txt
index 464a85302ec..273d8fc7968 100644
--- a/doc/device-tree-bindings/video/exynos-dp.txt
+++ b/doc/device-tree-bindings/video/exynos-dp.txt
@@ -30,9 +30,9 @@ Optional properties:
 		8(WHITE_GRAY_BALCKBAR_64),9(MOBILE_WHITEBAR_32),
 		10(MOBILE_WHITEBAR_64)
 	samsung,h-sync-polarity: Horizontal Sync polarity
-			CONFIG_SYS_LOW if defined, else CONFIG_SYS_HIGH
+			CFG_SYS_LOW if defined, else CONFIG_SYS_HIGH
 	samsung,v-sync-polarity: Vertical Sync polarity
-			CONFIG_SYS_LOW if defined, else CONFIG_SYS_HIGH
+			CFG_SYS_LOW if defined, else CONFIG_SYS_HIGH
 	samsung,interlaced: Progressive if 0, else Interlaced
 	samsung,color-space: input video data format
 		COLOR_RGB = 0, COLOR_YCBCR422 = 1, COLOR_YCBCR444 = 2
diff --git a/doc/device-tree-bindings/video/exynos-fb.txt b/doc/device-tree-bindings/video/exynos-fb.txt
index b022f6163f1..bff0cecfcfb 100644
--- a/doc/device-tree-bindings/video/exynos-fb.txt
+++ b/doc/device-tree-bindings/video/exynos-fb.txt
@@ -23,15 +23,15 @@ Board(panel specific):
 	samsung,vl-height: Height of display area in mm
 
 	samsung,vl-clkp: Clock polarity
-		CONFIG_SYS_LOW if defined, else CONFIG_SYS_HIGH
+		CFG_SYS_LOW if defined, else CONFIG_SYS_HIGH
 	samsung,vl-oep: Output Enable polarity
-		CONFIG_SYS_LOW if defined, else CONFIG_SYS_HIGH
+		CFG_SYS_LOW if defined, else CONFIG_SYS_HIGH
 	samsung,vl-hsp: Horizontal Sync polarity
-		CONFIG_SYS_LOW if defined, else CONFIG_SYS_HIGH
+		CFG_SYS_LOW if defined, else CONFIG_SYS_HIGH
 	samsung,vl-vsp: Vertical Sync polarity
-		CONFIG_SYS_LOW if defined, else CONFIG_SYS_HIGH
+		CFG_SYS_LOW if defined, else CONFIG_SYS_HIGH
 	samsung,vl-dp: Data polarity
-		CONFIG_SYS_LOW if defined, else CONFIG_SYS_HIGH
+		CFG_SYS_LOW if defined, else CONFIG_SYS_HIGH
 
 	samsung,vl-cmd-allow-len: Wait end of frame
 	samsung,winid: Window number on which data is to be displayed
diff --git a/doc/imx/common/imx5.txt b/doc/imx/common/imx5.txt
index ea0e144cedc..6c8c2e594fb 100644
--- a/doc/imx/common/imx5.txt
+++ b/doc/imx/common/imx5.txt
@@ -16,7 +16,7 @@ i.MX5x SoCs.
     of frequency deviation), avoiding system failure, or at least decreasing
     the likelihood of system failure.
 
-1.2 CONFIG_SYS_MAIN_PWR_ON: Trigger MAIN_PWR_ON upon startup.
+1.2 CFG_SYS_MAIN_PWR_ON: Trigger MAIN_PWR_ON upon startup.
     This option should be enabled for boards having a SYS_ON_OFF_CTL signal
     connected to GPIO1[23] and triggering the MAIN_PWR_ON signal like in the
     reference designs.
diff --git a/doc/usage/environment.rst b/doc/usage/environment.rst
index 15897f63dd9..83f210d2d05 100644
--- a/doc/usage/environment.rst
+++ b/doc/usage/environment.rst
@@ -162,7 +162,7 @@ bootm_low
     for use by the bootm command. See also "bootm_size"
     environment variable. Address defined by "bootm_low" is
     also the base of the initial memory mapping for the Linux
-    kernel -- see the description of CONFIG_SYS_BOOTMAPSZ and
+    kernel -- see the description of CFG_SYS_BOOTMAPSZ and
     bootm_mapsize.
 
 bootm_mapsize
@@ -170,7 +170,7 @@ bootm_mapsize
     This variable is given as a hexadecimal number and it
     defines the size of the memory region starting at base
     address bootm_low that is accessible by the Linux kernel
-    during early boot.  If unset, CONFIG_SYS_BOOTMAPSZ is used
+    during early boot.  If unset, CFG_SYS_BOOTMAPSZ is used
     as the default value if it is defined, and bootm_size is
     used otherwise.
 
@@ -228,7 +228,7 @@ initrd_high
     is usually what you want since it allows for
     maximum initrd size. If for some reason you want to
     make sure that the initrd image is loaded below the
-    CONFIG_SYS_BOOTMAPSZ limit, you can set this environment
+    CFG_SYS_BOOTMAPSZ limit, you can set this environment
     variable to a value of "no" or "off" or "0".
     Alternatively, you can set it to a maximum upper
     address to use (U-Boot will still check that it