diff options
| author | Rick Chen <[email protected]> | 2019-08-28 18:46:06 +0800 |
|---|---|---|
| committer | Andes <[email protected]> | 2019-09-03 09:31:03 +0800 |
| commit | 4fa4267d82d13eb45cc4202e4439de862e8cad0e (patch) | |
| tree | ec0822a0d677e1e2fc8c2d4491894373d5857d33 /drivers/cache/Kconfig | |
| parent | abd858e5754c0f1e71aa86abde049d9ee81fda3e (diff) | |
dm: cache: add v5l2 cache controller driver
Add a v5l2 cache controller driver that is usually found on
Andes RISC-V ae350 platform. It will parse the cache settings
from the dtb.
In this version tag and data ram control timing can be adjusted
by the requirement from the dtb.
Signed-off-by: Rick Chen <[email protected]>
Cc: KC Lin <[email protected]>
Reviewed-by: Bin Meng <[email protected]>
Diffstat (limited to 'drivers/cache/Kconfig')
| -rw-r--r-- | drivers/cache/Kconfig | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/drivers/cache/Kconfig b/drivers/cache/Kconfig index 24def7ac0fe..629039e7a88 100644 --- a/drivers/cache/Kconfig +++ b/drivers/cache/Kconfig @@ -22,4 +22,13 @@ config L2X0_CACHE ARMv7(32-bit) devices. The driver configures the cache settings found in the device tree. +config V5L2_CACHE + bool "Andes V5L2 cache driver" + select CACHE + depends on RISCV_NDS_CACHE + help + Support Andes V5L2 cache controller in AE350 platform. + It will configure tag and data ram timing control from the + device tree and enable L2 cache. + endmenu |