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authorTom Rini <[email protected]>2025-07-03 08:26:50 -0600
committerTom Rini <[email protected]>2025-07-03 08:26:50 -0600
commit1323b480a6fc053475901a90bdaece2ddcc47310 (patch)
treead95724d3b8a81e0992eb1a6dedb0c6c129f302c /drivers/cache
parent218db7bdbd0ea115c166f8bf18e1292c588beb10 (diff)
parentf62062a64daeb3f3b148372d0afae3821aff16de (diff)
Merge branch 'next' of https://source.denx.de/u-boot/custodians/u-boot-riscv into next
CI: https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/26936 - RISC-V: Add big-endian build support - Board: aclint_ipi: Support T-Head C900 CLINT - Board: mpfs_icicle: Implement board_fdt_blob_setup()/board_fit_config_name_match() - Driver: pinctrl: Port pin controller driver for T-Head TH1520 SoC - Driver: cache: Update dependency for ANDES_L2_CACHE
Diffstat (limited to 'drivers/cache')
-rw-r--r--drivers/cache/Kconfig1
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/cache/Kconfig b/drivers/cache/Kconfig
index 4f358657444..f5bcd406a50 100644
--- a/drivers/cache/Kconfig
+++ b/drivers/cache/Kconfig
@@ -24,6 +24,7 @@ config L2X0_CACHE
config ANDES_L2_CACHE
bool "Andes L2 cache driver"
+ depends on RISCV
select CACHE
help
Support Andes L2 cache controller in AE350 platform.