Merge tag 'v2021.10-rc4' into next

Prepare v2021.10-rc4

Signed-off-by: Tom Rini <[email protected]>

# gpg: Signature made Tue 14 Sep 2021 06:58:32 PM EDT
# gpg:                using RSA key 1A3C7F70E08FAB1707809BBF147C39FF9634B72C
# gpg: Good signature from "Thomas Rini <[email protected]>" [ultimate]

# Conflicts:
#	board/Arcturus/ucp1020/spl.c
#	cmd/mvebu/Kconfig
#	common/Kconfig.boot
#	common/image-fit.c
#	configs/UCP1020_defconfig
#	configs/sifive_unmatched_defconfig
#	drivers/pci/Kconfig
#	include/configs/UCP1020.h
#	include/configs/sifive-unmatched.h
#	lib/Makefile
#	scripts/config_whitelist.txt

3 files changed, 83 insertions, 0 deletions

diff --git a/drivers/cache/Kconfig b/drivers/cache/Kconfig
index 1e452ad6d9f..40f41a817c9 100644
--- a/drivers/cache/Kconfig
+++ b/drivers/cache/Kconfig
@@ -39,4 +39,11 @@ config NCORE_CACHE
 	  controller. The driver initializes cache directories and coherent
 	  agent interfaces.
 
+config SIFIVE_CCACHE
+	bool "SiFive composable cache"
+	select CACHE
+	help
+	  This driver is for SiFive Composable L2/L3 cache. It enables cache
+	  ways of composable cache.
+
 endmenu
diff --git a/drivers/cache/Makefile b/drivers/cache/Makefile
index fed50be3f98..ad765774e32 100644
--- a/drivers/cache/Makefile
+++ b/drivers/cache/Makefile
@@ -4,3 +4,4 @@ obj-$(CONFIG_SANDBOX) += sandbox_cache.o
 obj-$(CONFIG_L2X0_CACHE) += cache-l2x0.o
 obj-$(CONFIG_NCORE_CACHE) += cache-ncore.o
 obj-$(CONFIG_V5L2_CACHE) += cache-v5l2.o
+obj-$(CONFIG_SIFIVE_CCACHE) += cache-sifive-ccache.o
diff --git a/drivers/cache/cache-sifive-ccache.c b/drivers/cache/cache-sifive-ccache.c
new file mode 100644
index 00000000000..76c0ab26ae3
--- /dev/null
+++ b/drivers/cache/cache-sifive-ccache.c
@@ -0,0 +1,75 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2021 SiFive
+ */
+
+#include <common.h>
+#include <cache.h>
+#include <dm.h>
+#include <asm/io.h>
+#include <dm/device.h>
+#include <linux/bitfield.h>
+
+#define SIFIVE_CCACHE_CONFIG		0x000
+#define SIFIVE_CCACHE_CONFIG_WAYS	GENMASK(15, 8)
+
+#define SIFIVE_CCACHE_WAY_ENABLE	0x008
+
+struct sifive_ccache {
+	void __iomem *base;
+};
+
+static int sifive_ccache_enable(struct udevice *dev)
+{
+	struct sifive_ccache *priv = dev_get_priv(dev);
+	u32 config;
+	u32 ways;
+
+	/* Enable all ways of composable cache */
+	config = readl(priv->base + SIFIVE_CCACHE_CONFIG);
+	ways = FIELD_GET(SIFIVE_CCACHE_CONFIG_WAYS, config);
+
+	writel(ways - 1, priv->base + SIFIVE_CCACHE_WAY_ENABLE);
+
+	return 0;
+}
+
+static int sifive_ccache_get_info(struct udevice *dev, struct cache_info *info)
+{
+	struct sifive_ccache *priv = dev_get_priv(dev);
+
+	info->base = (phys_addr_t)priv->base;
+
+	return 0;
+}
+
+static const struct cache_ops sifive_ccache_ops = {
+	.enable = sifive_ccache_enable,
+	.get_info = sifive_ccache_get_info,
+};
+
+static int sifive_ccache_probe(struct udevice *dev)
+{
+	struct sifive_ccache *priv = dev_get_priv(dev);
+
+	priv->base = dev_read_addr_ptr(dev);
+	if (!priv->base)
+		return -EINVAL;
+
+	return 0;
+}
+
+static const struct udevice_id sifive_ccache_ids[] = {
+	{ .compatible = "sifive,fu540-c000-ccache" },
+	{ .compatible = "sifive,fu740-c000-ccache" },
+	{}
+};
+
+U_BOOT_DRIVER(sifive_ccache) = {
+	.name = "sifive_ccache",
+	.id = UCLASS_CACHE,
+	.of_match = sifive_ccache_ids,
+	.probe = sifive_ccache_probe,
+	.priv_auto = sizeof(struct sifive_ccache),
+	.ops = &sifive_ccache_ops,
+};