diff options
| author | Heinrich Schuchardt <[email protected]> | 2021-09-04 10:36:49 +0200 |
|---|---|---|
| committer | Leo Yu-Chi Liang <[email protected]> | 2021-09-07 10:34:29 +0800 |
| commit | f6431e8fb358e2fdd01692604cd5796a1b7c10a0 (patch) | |
| tree | 90157a7b970c89fc1bd9f881b5ad1ef9c0fdbb43 /drivers/cache | |
| parent | 5b2d359d9a7c7ed8299b7df0d25a24491e2c3b16 (diff) | |
riscv: show code leading to exception
To make analyzing exceptions easier output the code that leads to it.
We already do the same on the ARM platform.
Here is an example:
=> exception ebreak
Unhandled exception: Breakpoint
EPC: 000000008ff5d50e RA: 000000008ff5d62c TVAL: 0000000000000000
EPC: 000000008020b50e RA: 000000008020b62c reloc adjusted
Code: 2785 0693 07a0 dce3 fef6 47a5 d563 00e7 (9002)
To disassemble the code we can use the decodecode script:
$ echo 'Code: 2785 0693 07a0 dce3 fef6 47a5 d563 00e7 (9002)' | \
CROSS_COMPILE=riscv64-linux-gnu- scripts/decodecode
Code: 2785 0693 07a0 dce3 fef6 47a5 d563 00e7 (9002)
All code
========
0: 2785 addiw a5,a5,1
2: 07a00693 li a3,122
6: fef6dce3 bge a3,a5,0xfffffffffffffffe
a: 47a5 li a5,9
c: 00e7d563 bge a5,a4,0x16
10:* 9002 ebreak <-- trapping instruction
...
Code starting with the faulting instruction
===========================================
0: 9002 ebreak
...
As it is not always clear if the first 16 bits are at the start or in the
middle of a 32bit instruction it may become necessary to strip the first
u16 from the output before calling decodecode to get the correct
disassembled code.
Signed-off-by: Heinrich Schuchardt <[email protected]>
Reviewed-by: Bin Meng <[email protected]>
Reviewed-by: Sean Anderson <[email protected]>
Diffstat (limited to 'drivers/cache')
0 files changed, 0 insertions, 0 deletions
