diff options
| author | Tom Rini <[email protected]> | 2023-03-20 17:52:42 -0400 |
|---|---|---|
| committer | Tom Rini <[email protected]> | 2023-03-20 17:52:42 -0400 |
| commit | 51321493ebf029a9c3b33c02104f20fd5cb3a9be (patch) | |
| tree | f8e216759f6005bc9f2715232897cf1cd319fff4 /drivers/clk | |
| parent | 318af47668aa2347ca9bbf2114cb9af1d8739aca (diff) | |
| parent | d35a1392c5d17e067d16b7b096565b16af495f34 (diff) | |
Merge tag 'u-boot-rockchip-20230319' of https://source.denx.de/u-boot/custodians/u-boot-rockchip
- Fix for rockchip timer driver;
- Fix for rk3568 and rk3588 boot device and clock driver;
- Fix for rk3568 reset handler;
- Fix for rk3568 sdhci DLL at 52MHz;
Diffstat (limited to 'drivers/clk')
| -rw-r--r-- | drivers/clk/rockchip/clk_rk3568.c | 5 | ||||
| -rw-r--r-- | drivers/clk/rockchip/clk_rk3588.c | 4 |
2 files changed, 7 insertions, 2 deletions
diff --git a/drivers/clk/rockchip/clk_rk3568.c b/drivers/clk/rockchip/clk_rk3568.c index 99c195b3afe..1c6adc56f91 100644 --- a/drivers/clk/rockchip/clk_rk3568.c +++ b/drivers/clk/rockchip/clk_rk3568.c @@ -14,6 +14,7 @@ #include <asm/arch-rockchip/clock.h> #include <asm/arch-rockchip/hardware.h> #include <asm/io.h> +#include <dm/device-internal.h> #include <dm/lists.h> #include <dt-bindings/clock/rk3568-cru.h> @@ -424,6 +425,9 @@ static ulong rk3568_pmuclk_set_rate(struct clk *clk, ulong rate) case PCLK_PMU: ret = rk3568_pmu_set_pmuclk(priv, rate); break; + case CLK_PCIEPHY0_REF: + case CLK_PCIEPHY1_REF: + return 0; default: return -ENOENT; } @@ -2937,6 +2941,7 @@ static int rk3568_clk_bind(struct udevice *dev) glb_srst_fst); priv->glb_srst_snd_value = offsetof(struct rk3568_cru, glb_srsr_snd); + dev_set_priv(sys_child, priv); } #if CONFIG_IS_ENABLED(RESET_ROCKCHIP) diff --git a/drivers/clk/rockchip/clk_rk3588.c b/drivers/clk/rockchip/clk_rk3588.c index 5271d943483..a7df553e875 100644 --- a/drivers/clk/rockchip/clk_rk3588.c +++ b/drivers/clk/rockchip/clk_rk3588.c @@ -1558,7 +1558,7 @@ static ulong rk3588_clk_get_rate(struct clk *clk) #ifndef CONFIG_SPL_BUILD case CLK_AUX16M_0: case CLK_AUX16M_1: - rk3588_aux16m_get_clk(priv, clk->id); + rate = rk3588_aux16m_get_clk(priv, clk->id); break; case ACLK_VOP_ROOT: case ACLK_VOP: @@ -1707,7 +1707,7 @@ static ulong rk3588_clk_set_rate(struct clk *clk, ulong rate) #ifndef CONFIG_SPL_BUILD case CLK_AUX16M_0: case CLK_AUX16M_1: - rk3588_aux16m_set_clk(priv, clk->id, rate); + ret = rk3588_aux16m_set_clk(priv, clk->id, rate); break; case ACLK_VOP_ROOT: case ACLK_VOP: |