diff options
| author | Michal Simek <[email protected]> | 2024-04-16 08:55:19 +0200 |
|---|---|---|
| committer | Tom Rini <[email protected]> | 2024-04-22 11:01:48 -0600 |
| commit | 81f3a665ab2a63a31ec7a4d760b0ce8130f62a1d (patch) | |
| tree | ea17474c16b46c0710b48b1cf875bc608e9c7f9d /drivers/clk | |
| parent | 5a6cf7c5d54769d2500e796702f6d210907ea7e4 (diff) | |
common: Convert *.c/h from UTF-8 to ASCII enconfing
Convert UTF-8 chars to ASCII in cases where make sense. No Copyright or
names are converted.
Signed-off-by: Michal Simek <[email protected]>
Reviewed-by: Tom Rini <[email protected]>
Acked-by: Marek Behún <[email protected]>
Diffstat (limited to 'drivers/clk')
| -rw-r--r-- | drivers/clk/renesas/rzg2l-cpg.c | 6 | ||||
| -rw-r--r-- | drivers/clk/stm32/clk-stm32-core.h | 22 |
2 files changed, 14 insertions, 14 deletions
diff --git a/drivers/clk/renesas/rzg2l-cpg.c b/drivers/clk/renesas/rzg2l-cpg.c index dba009997a8..c8735d869cf 100644 --- a/drivers/clk/renesas/rzg2l-cpg.c +++ b/drivers/clk/renesas/rzg2l-cpg.c @@ -313,9 +313,9 @@ static ulong rzg2l_sdhi_clk_set_rate(struct udevice *dev, const struct cpg_core_ /* * As per the HW manual, we should not directly switch from 533 MHz to - * 400 MHz and vice versa. To change the setting from 2’b01 (533 MHz) - * to 2’b10 (400 MHz) or vice versa, Switch to 2’b11 (266 MHz) first, - * and then switch to the target setting (2’b01 (533 MHz) or 2’b10 + * 400 MHz and vice versa. To change the setting from 2'b01 (533 MHz) + * to 2'b10 (400 MHz) or vice versa, Switch to 2'b11 (266 MHz) first, + * and then switch to the target setting (2'b01 (533 MHz) or 2'b10 * (400 MHz)). */ if (new_sel != SEL_SDHI_266MHz && prev_sel != SEL_SDHI_266MHz) { diff --git a/drivers/clk/stm32/clk-stm32-core.h b/drivers/clk/stm32/clk-stm32-core.h index 53c2b467ab8..f9ef0702005 100644 --- a/drivers/clk/stm32/clk-stm32-core.h +++ b/drivers/clk/stm32/clk-stm32-core.h @@ -178,7 +178,7 @@ int stm32_rcc_init(struct udevice *dev, * ------------------------------ ---------- * Each peripheral requires a bus interface clock, named ckg_bus_perx - * (for peripheral ‘x’). + * (for peripheral `x'). * Some peripherals (SAI, UART...) need also a dedicated clock for their * communication interface, this clock is generally asynchronous with respect to * the bus interface clock, and is named kernel clock (ckg_ker_perx). @@ -188,16 +188,16 @@ int stm32_rcc_init(struct udevice *dev, * the bus or the Kernel was enable. * * Example: - * 1) enable the bus clock - * --> bus_clk ref_counting = 1, gate_ref_count = 1 - * 2) enable the kernel clock - * --> perx_ker_ck ref_counting = 1, gate_ref_count = 2 - * 3) disable kernel clock - * ---> perx_ker_ck ref_counting = 0, gate_ref_count = 1 - * ==> then i will not gate because gate_ref_count > 0 - * 4) disable bus clock - * --> bus_clk ref_counting = 0, gate_ref_count = 0 - * ==> then i can gate (write in the register) because + * 1) enable the bus clock + * --> bus_clk ref_counting = 1, gate_ref_count = 1 + * 2) enable the kernel clock + * --> perx_ker_ck ref_counting = 1, gate_ref_count = 2 + * 3) disable kernel clock + * ---> perx_ker_ck ref_counting = 0, gate_ref_count = 1 + * ==> then i will not gate because gate_ref_count > 0 + * 4) disable bus clock + * --> bus_clk ref_counting = 0, gate_ref_count = 0 + * ==> then i can gate (write in the register) because * gate_ref_count = 0 */ |