diff options
| author | Hai Pham <[email protected]> | 2023-01-26 21:06:04 +0100 |
|---|---|---|
| committer | Marek Vasut <[email protected]> | 2023-02-02 01:49:20 +0100 |
| commit | c287c184aea435ef17ff5d11c3e06540dd2db0d7 (patch) | |
| tree | 64c058ca72774f2245ade21dde16edbb27b9f9c7 /drivers/clk | |
| parent | a1ec0bbc282ca02175f9b5efb41c1bc4a16a9e9c (diff) | |
clk: renesas: Handle E3/D3 RPCSRC clock
The RPCSRC clock divider on R-Car D3 is very similar to the one on R-Car
E3, but uses a different pre-divider for the PLL0 parent. Add a new
macro to describe it, reusing the existing clock type for R-Car E3.
As both E3/D3 RPCSRC clock divider are different from the rest of R-Car
Gen3, keep the original implementation from Linux.
Based on Linux commit 40745482eec8 ("clk: renesas: r8a774c0: Add RPC
clocks") by Lad Prabhakar and 9d18f81b3535 ("clk: renesas: r8a77995: Add
RPC clocks") by Geert Uytterhoeven.
Signed-off-by: Hai Pham <[email protected]>
Signed-off-by: Marek Vasut <[email protected]> # Add D3 tweaks
Diffstat (limited to 'drivers/clk')
| -rw-r--r-- | drivers/clk/renesas/clk-rcar-gen3.c | 31 |
1 files changed, 31 insertions, 0 deletions
diff --git a/drivers/clk/renesas/clk-rcar-gen3.c b/drivers/clk/renesas/clk-rcar-gen3.c index 84bd7fe8b00..aea8b1e8390 100644 --- a/drivers/clk/renesas/clk-rcar-gen3.c +++ b/drivers/clk/renesas/clk-rcar-gen3.c @@ -358,6 +358,37 @@ static u64 gen3_clk_get_rate64(struct clk *clk) CPG_RPCCKCR_DIV_POST_MASK, cpg_rpcsrc_div_table, "RPCSRC"); + case CLK_TYPE_GEN3_D3_RPCSRC: + case CLK_TYPE_GEN3_E3_RPCSRC: + /* + * Register RPCSRC as fixed factor clock based on the + * MD[4:1] pins and CPG_RPCCKCR[4:3] register value for + * which has been set prior to booting the kernel. + */ + value = (readl(priv->base + CPG_RPCCKCR) & GENMASK(4, 3)) >> 3; + + switch (value) { + case 0: + div = 5; + break; + case 1: + div = 3; + break; + case 2: + div = core->div; + break; + case 3: + default: + div = 2; + break; + } + + rate = gen3_clk_get_rate64(&parent) / div; + debug("%s[%i] E3/D3 RPCSRC clk: parent=%i div=%u => rate=%llu\n", + __func__, __LINE__, (core->parent >> 16) & 0xffff, div, rate); + + return rate; + case CLK_TYPE_GEN3_RPC: case CLK_TYPE_GEN4_RPC: return rcar_clk_get_rate64_div_table(core->parent, |