diff options
| author | Tom Rini <[email protected]> | 2025-07-31 08:45:50 -0600 |
|---|---|---|
| committer | Tom Rini <[email protected]> | 2025-07-31 10:04:32 -0600 |
| commit | f5e968a28e7cdc2c4365f5a382e02f074ee03fac (patch) | |
| tree | 2f988c7102a977da562c28075e94e875ab5bcb94 /drivers/clk | |
| parent | eef444c38994aee9cd3c6e4df5791b5f7209c8d8 (diff) | |
| parent | e064db5fe77caaddb21a7793f266119ad89dd79a (diff) | |
Merge tag 'u-boot-stm32-20250731' of https://source.denx.de/u-boot/custodians/u-boot-stm
CI: https://source.denx.de/u-boot/custodians/u-boot-stm/-/pipelines/27236
- Add support for STM32 TIMERS and STM32 PWM on STM32MP25
- Add STM32MP13xx SPL and OpTee-OS start support
- Fix header misuse in stm32 reset drivers
- Fix STMicroelectronics spelling
- Fix clk-stm32h7 wrong macros used in register read
- Fix PRE_CON_BUF_ADDR on STM32MP13
- Fix clock identifier passed to struct scmi_clk_parent_set_in
- Fix stm32 reset for STM32F4/F7 and H7
- Enable OF_UPSTREAM_BUILD_VENDOR for stm32mp13_defconfig
- Add STM32MP23 SoC and stm32mp235f-dk board support
Diffstat (limited to 'drivers/clk')
| -rw-r--r-- | drivers/clk/clk_scmi.c | 4 | ||||
| -rw-r--r-- | drivers/clk/stm32/clk-stm32h7.c | 4 |
2 files changed, 4 insertions, 4 deletions
diff --git a/drivers/clk/clk_scmi.c b/drivers/clk/clk_scmi.c index cfb372e6190..0c9a81cabcc 100644 --- a/drivers/clk/clk_scmi.c +++ b/drivers/clk/clk_scmi.c @@ -336,8 +336,8 @@ static int scmi_clk_probe(struct udevice *dev) static int __scmi_clk_set_parent(struct clk *clk, struct clk *parent) { struct scmi_clk_parent_set_in in = { - .clock_id = clk->id, - .parent_clk = parent->id, + .clock_id = clk_get_id(clk), + .parent_clk = clk_get_id(parent), }; struct scmi_clk_parent_set_out out; struct scmi_msg msg = SCMI_MSG_IN(SCMI_PROTOCOL_ID_CLOCK, diff --git a/drivers/clk/stm32/clk-stm32h7.c b/drivers/clk/stm32/clk-stm32h7.c index aa3be414a29..df82db69738 100644 --- a/drivers/clk/stm32/clk-stm32h7.c +++ b/drivers/clk/stm32/clk-stm32h7.c @@ -549,8 +549,8 @@ static u32 stm32_get_PLL1_rate(struct stm32_rcc_regs *regs, divr1 = readl(®s->pll1divr) & RCC_PLL1DIVR_DIVR1_MASK; divr1 = (divr1 >> RCC_PLL1DIVR_DIVR1_SHIFT) + 1; - fracn1 = readl(®s->pll1fracr) & RCC_PLL1DIVR_DIVR1_MASK; - fracn1 = fracn1 & RCC_PLL1DIVR_DIVR1_SHIFT; + fracn1 = readl(®s->pll1fracr) & RCC_PLL1FRACR_FRACN1_MASK; + fracn1 = (fracn1 >> RCC_PLL1FRACR_FRACN1_SHIFT) + 1; vco = (pllsrc / divm1) * divn1; rate = (pllsrc * fracn1) / (divm1 * 8192); |