Merge tag 'u-boot-socfpga-next-20250930' of https://source.denx.de/u-boot/custodians/u-boot-socfpga into next

SoCFPGA updates for v2025.10:

CI: https://source.denx.de/u-boot/custodians/u-boot-socfpga/-/pipelines/27762

This pull request brings a set of updates across SoCFPGA platforms
covering Agilex5, Agilex7, N5X, and Stratix10. The changes include:

* Agilex5 enhancements:
  - USB3.1 enablement and DWC3 host driver support
  - System Manager register configuration for USB3
  - Watchdog timeout increase and SDMMC clock API integration
  - dcache handling improvements in SMC mailbox path
  - Enable SPL_SYS_DCACHE_OFF in defconfig

* Clock driver improvements:
  - Introduce dt-bindings header for Agilex clocks
  - Add enable/disable API and EMAC clock selection fixes
  - Replace manual shifts with FIELD_GET usage

* DDR updates:
  - IOSSM mailbox compatibility check
  - Correct DDR calibration status handling

* Device tree changes:
  - Agilex5: disable cache allocation for reads
  - Stratix10: add NAND IP node
  - Enable driver model watchdog
  - Enable USB3.1 node for Agilex5

* Config cleanups:
  - Simplify Agilex7 VAB defconfig
  - Remove obsolete SYS_BOOTM_LEN from N5X VAB config
  - Enable CRC32 support for SoCFPGA
  - Increase USB hub debounce timeout

Overall this set improves reliability of DDR and cache flows,
adds missing USB and MMC features for Agilex5, and refines clock
and configuration handling across platforms.

This patch set has been tested on Agilex 5 devkit, and Agilex devkit.

3 files changed, 28 insertions, 4 deletions

diff --git a/drivers/ddr/altera/iossm_mailbox.c b/drivers/ddr/altera/iossm_mailbox.c
index 21f94959a04..2a2f86a650e 100644
--- a/drivers/ddr/altera/iossm_mailbox.c
+++ b/drivers/ddr/altera/iossm_mailbox.c
@@ -38,6 +38,8 @@
 #define IOSSM_STATUS_CMD_RESPONSE_ERROR(n)	FIELD_GET(IOSSM_STATUS_CMD_RESPONSE_ERROR_MASK, n)
 #define IOSSM_STATUS_GENERAL_ERROR_MASK		GENMASK(4, 1)
 #define IOSSM_STATUS_GENERAL_ERROR(n)		FIELD_GET(IOSSM_STATUS_GENERAL_ERROR_MASK, n)
+#define IOSSM_MAILBOX_SPEC_VERSION_MASK		GENMASK(2, 0)
+#define IOSSM_MAILBOX_SPEC_VERSION(n)		FIELD_GET(IOSSM_MAILBOX_SPEC_VERSION_MASK, n)
 
 /* Offset of Mailbox Read-only Registers  */
 #define IOSSM_MAILBOX_HEADER_OFFSET			0x0
@@ -383,6 +385,23 @@ err:
 	return ret;
 }
 
+static bool is_mailbox_spec_compatible(struct io96b_info *io96b_ctrl)
+{
+	u32 mailbox_header;
+	u8 mailbox_spec_ver;
+
+	mailbox_header = readl(io96b_ctrl->io96b[0].io96b_csr_addr +
+				IOSSM_MAILBOX_HEADER_OFFSET);
+	mailbox_spec_ver = IOSSM_MAILBOX_SPEC_VERSION(mailbox_header);
+	printf("%s: IOSSM mailbox version: %d\n", __func__, mailbox_spec_ver);
+
+	/* for now there are two mailbox spec versions, 0 and 1; only version 1 is compatible */
+	if (!mailbox_spec_ver)
+		return false;
+
+	return true;
+}
+
 /*
  * Initial function to be called to set memory interface IP type and instance ID
  * IP type and instance ID need to be determined before sending mailbox command
@@ -392,6 +411,11 @@ void io96b_mb_init(struct io96b_info *io96b_ctrl)
 	int i, j;
 	u32 mem_intf_info_0, mem_intf_info_1;
 
+	if (!is_mailbox_spec_compatible(io96b_ctrl)) {
+		printf("DDR: Failed to get compatible mailbox version\n");
+		hang();
+	}
+
 	debug("%s: num_instance %d\n", __func__, io96b_ctrl->num_instance);
 
 	for (i = 0; i < io96b_ctrl->num_instance; i++) {
diff --git a/drivers/ddr/altera/sdram_soc64.c b/drivers/ddr/altera/sdram_soc64.c
index f8fc92060db..2d0093c591c 100644
--- a/drivers/ddr/altera/sdram_soc64.c
+++ b/drivers/ddr/altera/sdram_soc64.c
@@ -85,11 +85,11 @@ int emif_reset(struct altera_sdram_plat *plat)
 	debug("DDR: Triggerring emif reset\n");
 	hmc_ecc_writel(plat, DDR_HMC_CORE2SEQ_INT_REQ, RSTHANDSHAKECTRL);
 
-	/* if seq2core[3] = 0, we are good */
+	/* if seq2core[2:0] = 0b0000_0111, we are good */
 	ret = wait_for_bit_le32((const void *)(plat->hmc +
 				 RSTHANDSHAKESTAT),
-				 DDR_HMC_SEQ2CORE_INT_RESP_MASK,
-				 false, 1000, false);
+				 DDR_HMC_SEQ2CORE_INT_REQ_ACK_MASK,
+				 true, 1000, false);
 	if (ret) {
 		printf("DDR: failed to get ack from EMIF\n");
 		return ret;
diff --git a/drivers/ddr/altera/sdram_soc64.h b/drivers/ddr/altera/sdram_soc64.h
index 6031cef560e..6fe0653922c 100644
--- a/drivers/ddr/altera/sdram_soc64.h
+++ b/drivers/ddr/altera/sdram_soc64.h
@@ -77,7 +77,7 @@ struct altera_sdram_plat {
 #define DDR_HMC_INTMODE_INTMODE_SET_MSK		BIT(0)
 #define DDR_HMC_RSTHANDSHAKE_MASK		0x0000000f
 #define DDR_HMC_CORE2SEQ_INT_REQ		0x0000000f
-#define DDR_HMC_SEQ2CORE_INT_RESP_MASK		BIT(3)
+#define DDR_HMC_SEQ2CORE_INT_REQ_ACK_MASK	GENMASK(2, 0)
 #define DDR_HMC_HPSINTFCSEL_ENABLE_MASK		0x001f1f1f
 
 #define	DDR_HMC_ERRINTEN_INTMASK				\