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authorTejas Bhumkar <[email protected]>2023-09-15 10:20:43 +0530
committerMichal Simek <[email protected]>2023-09-21 13:20:11 +0200
commite31d707d8b591973560cb656d152a154993b1d74 (patch)
treece00d9c8a42ae71afea4c3e7658355cf8ed993f2 /drivers/net
parent1ae4a07c2bac18663b2cff003b360256bbb758dc (diff)
net: phy: xilinx-gmii2rgmii: Removed hardcoded phy address 0 for bridge
Current code expects bridge phy address at 0 which is not correct expectation because bridge phy address is configurable. That's why update the code to read reg property to figure it out where bridge is and use it in phy creation code. Signed-off-by: Tejas Bhumkar <[email protected]> Signed-off-by: Michal Simek <[email protected]> Link: https://lore.kernel.org/r/[email protected]
Diffstat (limited to 'drivers/net')
-rw-r--r--drivers/net/phy/phy.c5
1 files changed, 4 insertions, 1 deletions
diff --git a/drivers/net/phy/phy.c b/drivers/net/phy/phy.c
index d50fd505e51..63b3e46f101 100644
--- a/drivers/net/phy/phy.c
+++ b/drivers/net/phy/phy.c
@@ -807,7 +807,10 @@ static struct phy_device *phy_connect_gmii2rgmii(struct mii_dev *bus,
ofnode_for_each_subnode(node, dev_ofnode(dev)) {
node = ofnode_by_compatible(node, "xlnx,gmii-to-rgmii-1.0");
if (ofnode_valid(node)) {
- phydev = phy_device_create(bus, 0,
+ int gmiirgmii_phyaddr;
+
+ gmiirgmii_phyaddr = ofnode_read_u32_default(node, "reg", 0);
+ phydev = phy_device_create(bus, gmiirgmii_phyaddr,
PHY_GMII2RGMII_ID, false);
if (phydev)
phydev->node = node;