Merge tag 'xilinx-for-v2020.10' of https://gitlab.denx.de/u-boot/custodians/u-boot-microblaze into next

Xilinx changes for v2020.10

Versal:
- xspi bootmode fix
- Removing one clock from clk driver
- Align u-boot memory setting with OS by default
- Map TCM and OCM by default

ZynqMP:
- Minor DT improvements
- Reduce console buffer for mini configurations
- Add fix for AMS
- Add support for XDP platform

Zynq:
- Support for AES engine
- Enable bigger memory test by default
- Extend documentation for SD preparation
- Use different freq for Topic miami board

mmc:
- minor GD pointer removal

net:
- Support fixed-link cases by zynq gem
- Fix phy looking loop in axi enet driver

spi:
- Cleanup global macros for xilinx spi drivers

firmware:
- Add support for pmufw reloading

fpga:
- Improve error status reporting

common:
- Remove 4kB addition space for FDT allocation

5 files changed, 15 insertions, 7 deletions

diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c
index 9ae2db033e6..992180df869 100644
--- a/drivers/net/fec_mxc.c
+++ b/drivers/net/fec_mxc.c
@@ -1294,7 +1294,7 @@ static const struct eth_ops fecmxc_ops = {
 	.read_rom_hwaddr	= fecmxc_read_rom_hwaddr,
 };
 
-static int device_get_phy_addr(struct udevice *dev)
+static int device_get_phy_addr(struct fec_priv *priv, struct udevice *dev)
 {
 	struct ofnode_phandle_args phandle_args;
 	int reg;
@@ -1305,6 +1305,8 @@ static int device_get_phy_addr(struct udevice *dev)
 		return -ENODEV;
 	}
 
+	priv->phy_of_node = phandle_args.node;
+
 	reg = ofnode_read_u32_default(phandle_args.node, "reg", 0);
 
 	return reg;
@@ -1315,7 +1317,7 @@ static int fec_phy_init(struct fec_priv *priv, struct udevice *dev)
 	struct phy_device *phydev;
 	int addr;
 
-	addr = device_get_phy_addr(dev);
+	addr = device_get_phy_addr(priv, dev);
 #ifdef CONFIG_FEC_MXC_PHYADDR
 	addr = CONFIG_FEC_MXC_PHYADDR;
 #endif
@@ -1325,6 +1327,7 @@ static int fec_phy_init(struct fec_priv *priv, struct udevice *dev)
 		return -ENODEV;
 
 	priv->phydev = phydev;
+	priv->phydev->node = priv->phy_of_node;
 	phy_config(phydev);
 
 	return 0;
diff --git a/drivers/net/fec_mxc.h b/drivers/net/fec_mxc.h
index 0e8f08a51a1..659d62646f8 100644
--- a/drivers/net/fec_mxc.h
+++ b/drivers/net/fec_mxc.h
@@ -250,6 +250,7 @@ struct fec_priv {
 	struct mii_dev *bus;
 #ifdef CONFIG_PHYLIB
 	struct phy_device *phydev;
+	ofnode phy_of_node;
 #else
 	int phy_id;
 	int (*mii_postcall)(int);
diff --git a/drivers/net/phy/atheros.c b/drivers/net/phy/atheros.c
index 13f7275d170..f922fecd6b5 100644
--- a/drivers/net/phy/atheros.c
+++ b/drivers/net/phy/atheros.c
@@ -275,11 +275,10 @@ static int ar803x_of_init(struct phy_device *phydev)
 		 * Fixup for the AR8035 which only has two bits. The two
 		 * remaining bits map to the same frequencies.
 		 */
-		if (phydev->drv->uid == AR8035_PHY_ID) {
-			u16 clear = AR803x_CLK_25M_MASK & AR8035_CLK_25M_MASK;
 
-			priv->clk_25m_mask &= ~clear;
-			priv->clk_25m_reg &= ~clear;
+		if (phydev->drv->uid == AR8035_PHY_ID) {
+			priv->clk_25m_reg &= AR8035_CLK_25M_MASK;
+			priv->clk_25m_mask &= AR8035_CLK_25M_MASK;
 		}
 	}
 
diff --git a/drivers/net/xilinx_axi_emac.c b/drivers/net/xilinx_axi_emac.c
index d0683db80d8..2cd55967684 100644
--- a/drivers/net/xilinx_axi_emac.c
+++ b/drivers/net/xilinx_axi_emac.c
@@ -244,7 +244,8 @@ static u32 phywrite(struct axidma_priv *priv, u32 phyaddress, u32 registernum,
 static int axiemac_phy_init(struct udevice *dev)
 {
 	u16 phyreg;
-	u32 i, ret;
+	int i;
+	u32 ret;
 	struct axidma_priv *priv = dev_get_priv(dev);
 	struct axi_regs *regs = priv->iobase;
 	struct phy_device *phydev;
diff --git a/drivers/net/zynq_gem.c b/drivers/net/zynq_gem.c
index 412daf7d58b..da4b6fba9ff 100644
--- a/drivers/net/zynq_gem.c
+++ b/drivers/net/zynq_gem.c
@@ -451,8 +451,12 @@ static int zynq_gem_init(struct udevice *dev)
 		nwconfig |= ZYNQ_GEM_NWCFG_SGMII_ENBL |
 			    ZYNQ_GEM_NWCFG_PCS_SEL;
 #ifdef CONFIG_ARM64
+	if (priv->phydev->phy_id != PHY_FIXED_ID)
 		writel(readl(&regs->pcscntrl) | ZYNQ_GEM_PCS_CTL_ANEG_ENBL,
 		       &regs->pcscntrl);
+	else
+		writel(readl(&regs->pcscntrl) & ~ZYNQ_GEM_PCS_CTL_ANEG_ENBL,
+		       &regs->pcscntrl);
 #endif
 	}