summaryrefslogtreecommitdiff
path: root/drivers/pci
diff options
context:
space:
mode:
authorGeorge McCollister <[email protected]>2026-01-30 09:38:05 -0600
committerTom Rini <[email protected]>2026-02-04 10:40:28 -0600
commit795b1fd2dff8a8abc464c9f9a85e0b11966bbd1b (patch)
tree815b9e20734d4f2f3230e1631b02a6a179821610 /drivers/pci
parent3d07fe1390b352b897683f3eaf7ee62786474144 (diff)
pci: pcie_cdns_ti: Add PCIe support for J722S SoC
TI's J722S SoC has one instance of PCIe namely PCIe0 which is a Gen3 single lane PCIe controller. Add support for the "ti,j722s-pcie-host" compatible specific to J722S SoC. Based on: https://lore.kernel.org/all/[email protected]/ Signed-off-by: George McCollister <[email protected]> Tested-by: Bryan Brattlof <[email protected]>
Diffstat (limited to 'drivers/pci')
-rw-r--r--drivers/pci/pcie_cdns_ti.c9
1 files changed, 9 insertions, 0 deletions
diff --git a/drivers/pci/pcie_cdns_ti.c b/drivers/pci/pcie_cdns_ti.c
index ff56ba3930c..38804f1c09c 100644
--- a/drivers/pci/pcie_cdns_ti.c
+++ b/drivers/pci/pcie_cdns_ti.c
@@ -855,6 +855,11 @@ static const struct pcie_cdns_ti_data am64_pcie_rc_data = {
.max_lanes = 1,
};
+static const struct pcie_cdns_ti_data j722s_pcie_rc_data = {
+ .mode = PCIE_MODE_RC,
+ .max_lanes = 1,
+};
+
static const struct udevice_id pcie_cdns_ti_ids[] = {
{
.compatible = "ti,j7200-pcie-host",
@@ -864,6 +869,10 @@ static const struct udevice_id pcie_cdns_ti_ids[] = {
.compatible = "ti,am64-pcie-host",
.data = (ulong)&am64_pcie_rc_data,
},
+ {
+ .compatible = "ti,j722s-pcie-host",
+ .data = (ulong)&j722s_pcie_rc_data,
+ },
{},
};