diff options
| author | Marek Vasut <[email protected]> | 2025-08-06 21:23:54 +0200 |
|---|---|---|
| committer | Marek Vasut <[email protected]> | 2025-08-17 14:41:23 +0200 |
| commit | 93297f1f9bb5e21149fc344aaddf7cf2b7e1fb8f (patch) | |
| tree | 9ff6fb7bd52514b4d1bfa28616a8f7eae5f3aa55 /drivers/pci | |
| parent | 0c558bbad9e7581808b358091d1fd979f860e8ac (diff) | |
pci: pcie-rcar-gen4: Fix PHY initialization
R-Car V4H Reference Manual R19UH0186EJ0130 Rev.1.30 Apr. 21, 2025
page 4581 Figure 104.3b Initial Setting of PCIEC(example) middle
of the figure indicates that fourth write into register 0x148 [2:0]
is 0x3 or GENMASK(1, 0). The current code writes GENMASK(11, 0)
which is a typo. Fix the typo.
Fixes: be3dd0dc2fd9 ("pci: pcie-rcar-gen4: Add Renesas R-Car Gen4 DW PCIe controller driver")
Signed-off-by: Marek Vasut <[email protected]>
Diffstat (limited to 'drivers/pci')
| -rw-r--r-- | drivers/pci/pci-rcar-gen4.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/pci/pci-rcar-gen4.c b/drivers/pci/pci-rcar-gen4.c index 87cd69f989d..41f0d958447 100644 --- a/drivers/pci/pci-rcar-gen4.c +++ b/drivers/pci/pci-rcar-gen4.c @@ -235,7 +235,7 @@ static int rcar_gen4_pcie_ltssm_control(struct rcar_gen4_pcie *rcar, bool enable clrsetbits_le32(rcar->phy_base + 0x148, GENMASK(23, 22), BIT(22)); clrsetbits_le32(rcar->phy_base + 0x148, GENMASK(18, 16), GENMASK(17, 16)); clrsetbits_le32(rcar->phy_base + 0x148, GENMASK(7, 6), BIT(6)); - clrsetbits_le32(rcar->phy_base + 0x148, GENMASK(2, 0), GENMASK(11, 0)); + clrsetbits_le32(rcar->phy_base + 0x148, GENMASK(2, 0), GENMASK(1, 0)); clrsetbits_le32(rcar->phy_base + 0x1d4, GENMASK(16, 15), GENMASK(16, 15)); clrsetbits_le32(rcar->phy_base + 0x514, BIT(26), BIT(26)); clrsetbits_le32(rcar->phy_base + 0x0f8, BIT(16), 0); |