diff options
| author | Tom Rini <[email protected]> | 2026-03-16 08:24:18 -0600 |
|---|---|---|
| committer | Tom Rini <[email protected]> | 2026-03-16 08:24:18 -0600 |
| commit | 841856ed9675b26ec517fdd00b5cc0aef8db508e (patch) | |
| tree | 3c81d0a3094b9b128737a80c551bcd0dd6ed5d07 /drivers/phy | |
| parent | fa3a11fcf01a27f038789f4ef36d0414fe78b493 (diff) | |
| parent | 6230a595a733e381ecdbe35199d255f3d5801955 (diff) | |
Merge patch series "Add PCIe Boot support for TI J784S4 SoC"
Siddharth Vadapalli <[email protected]> says:
This series adds PCIe endpoint boot support for the TI J784S4 SoC.
Series is based on commit f9ffeec4bdc ("board: toradex: Make A53 get RAM
size from DT in K3 boards") of the master branch of U-Boot.
PCIe Boot Logs (J784S4-EVM running Linux as Root-Complex transfers
bootloaders to another J784S4-EVM configured for PCIe Boot):
https://gist.github.com/Siddharth-Vadapalli-at-TI/2d157003818441fe79a139d0dec1058a
Link: https://lore.kernel.org/r/[email protected]
Diffstat (limited to 'drivers/phy')
| -rw-r--r-- | drivers/phy/cadence/Kconfig | 7 | ||||
| -rw-r--r-- | drivers/phy/ti/Kconfig | 10 |
2 files changed, 17 insertions, 0 deletions
diff --git a/drivers/phy/cadence/Kconfig b/drivers/phy/cadence/Kconfig index 549ddbf5046..8c0ab80fbbc 100644 --- a/drivers/phy/cadence/Kconfig +++ b/drivers/phy/cadence/Kconfig @@ -9,3 +9,10 @@ config PHY_CADENCE_TORRENT depends on DM_RESET help Enable this to support the Cadence Torrent PHY driver + +config SPL_PHY_CADENCE_TORRENT + bool "Cadence Torrent PHY Driver" + depends on SPL_DM_RESET + help + Enable this to support the Cadence Torrent PHY driver at SPL + stage. diff --git a/drivers/phy/ti/Kconfig b/drivers/phy/ti/Kconfig index 111085f235d..df750b26d66 100644 --- a/drivers/phy/ti/Kconfig +++ b/drivers/phy/ti/Kconfig @@ -7,3 +7,13 @@ config PHY_J721E_WIZ signals to the SERDES (Sierra/Torrent). This driver configures three clock selects (pll0, pll1, dig) and resets for each of the lanes. + +config SPL_PHY_J721E_WIZ + bool "TI J721E WIZ (SERDES Wrapper) support" + depends on ARCH_K3 + help + This option enables support for WIZ module present in TI's J721E + SoC at SPL stage. WIZ is a serdes wrapper used to configure some + of the input signals to the SERDES (Sierra/Torrent). This driver + configures three clock selects (pll0, pll1, dig) and resets for + each of the lanes. |