diff options
| author | Sean Anderson <[email protected]> | 2026-01-06 16:54:59 -0500 |
|---|---|---|
| committer | Michal Simek <[email protected]> | 2026-01-12 13:01:27 +0100 |
| commit | 8c3e514d66def2a0f20cdc1cfef4d58542444576 (patch) | |
| tree | c999f9f48543a25c1d0fa3a227d9ea879f025dd7 /drivers/phy | |
| parent | 0320459cbf857f4bc340d3a500a38a57218768d5 (diff) | |
phy: zynqmp: Enable reference clock correctly
Lanes can use other lanes' reference clocks, as determined by refclk.
Use refclk to determine the clock to enable/disable instead of always
using the lane's own reference clock. This ensures the clock selected in
xpsgtr_configure_pll is the one enabled.
For the other half of the equation, always program REF_CLK_SEL even when
we are selecting the lane's own clock. This ensures that Linux's idea of
the reference clock matches the hardware. We use the "local" clock mux
for this instead of going through the ref clock network.
Signed-off-by: Sean Anderson <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Vinod Koul <[email protected]>
[ Linux commit 687d6bccb28238fcfa65f7c1badfdfeac498c428 ]
Fixes: 1d78d683496 ("phy: zynqmp: Add serdes/psgtr driver")
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Michal Simek <[email protected]>
Diffstat (limited to 'drivers/phy')
| -rw-r--r-- | drivers/phy/phy-zynqmp.c | 10 |
1 files changed, 6 insertions, 4 deletions
diff --git a/drivers/phy/phy-zynqmp.c b/drivers/phy/phy-zynqmp.c index 7151402666b..706903c5b52 100644 --- a/drivers/phy/phy-zynqmp.c +++ b/drivers/phy/phy-zynqmp.c @@ -82,7 +82,8 @@ /* Reference clock selection parameters */ #define L0_Ln_REF_CLK_SEL(n) (0x2860 + (n) * 4) -#define L0_REF_CLK_SEL_MASK 0x8f +#define L0_REF_CLK_LCL_SEL BIT(7) +#define L0_REF_CLK_SEL_MASK 0x9f /* Calibration digital logic parameters */ #define L3_TM_CALIB_DIG19 0xec4c @@ -303,11 +304,12 @@ static void xpsgtr_configure_pll(struct xpsgtr_phy *gtr_phy) PLL_FREQ_MASK, ssc->pll_ref_clk); /* Enable lane clock sharing, if required */ - if (gtr_phy->refclk != gtr_phy->lane) { - /* Lane3 Ref Clock Selection Register */ + if (gtr_phy->refclk == gtr_phy->lane) + xpsgtr_clr_set(gtr_phy->dev, L0_Ln_REF_CLK_SEL(gtr_phy->lane), + L0_REF_CLK_SEL_MASK, L0_REF_CLK_LCL_SEL); + else xpsgtr_clr_set(gtr_phy->dev, L0_Ln_REF_CLK_SEL(gtr_phy->lane), L0_REF_CLK_SEL_MASK, 1 << gtr_phy->refclk); - } /* SSC step size [7:0] */ xpsgtr_clr_set_phy(gtr_phy, L0_PLL_SS_STEP_SIZE_0_LSB, |