diff options
| author | Tom Rini <[email protected]> | 2025-03-26 14:07:37 -0600 |
|---|---|---|
| committer | Tom Rini <[email protected]> | 2025-03-26 14:07:37 -0600 |
| commit | 4adbf64ff8d8c730223fd8ae299d770bebb6fe86 (patch) | |
| tree | 7099e53be77df8a3a0e1ae122e8164a2d4f7cebf /drivers/pinctrl | |
| parent | df11ac859d366d96f749f2b9c3d2d5c564b325bc (diff) | |
| parent | 03f61b153965101f21783e8e6a1e5e86496598ff (diff) | |
Merge branch 'staging' of https://source.denx.de/u-boot/custodians/u-boot-tegra into next
- More Tegra video improvements
Diffstat (limited to 'drivers/pinctrl')
| -rw-r--r-- | drivers/pinctrl/tegra/pinctrl-tegra.c | 34 |
1 files changed, 17 insertions, 17 deletions
diff --git a/drivers/pinctrl/tegra/pinctrl-tegra.c b/drivers/pinctrl/tegra/pinctrl-tegra.c index e6b957f5537..b04be168bc8 100644 --- a/drivers/pinctrl/tegra/pinctrl-tegra.c +++ b/drivers/pinctrl/tegra/pinctrl-tegra.c @@ -23,18 +23,18 @@ static void tegra_pinctrl_set_drive(struct udevice *config, int drvcnt) return; } - drive_group[0].slwf = dev_read_u32_default(config, "nvidia,slew-rate-falling", 0); - drive_group[0].slwr = dev_read_u32_default(config, "nvidia,slew-rate-rising", 0); - drive_group[0].drvup = dev_read_u32_default(config, "nvidia,pull-up-strength", 0); - drive_group[0].drvdn = dev_read_u32_default(config, "nvidia,pull-down-strength", 0); + drive_group[0].slwf = dev_read_u32_default(config, "nvidia,slew-rate-falling", PMUX_SLWF_NONE); + drive_group[0].slwr = dev_read_u32_default(config, "nvidia,slew-rate-rising", PMUX_SLWR_NONE); + drive_group[0].drvup = dev_read_u32_default(config, "nvidia,pull-up-strength", PMUX_DRVUP_NONE); + drive_group[0].drvdn = dev_read_u32_default(config, "nvidia,pull-down-strength", PMUX_DRVDN_NONE); #ifdef TEGRA_PMX_GRPS_HAVE_LPMD - drive_group[0].lpmd = dev_read_u32_default(config, "nvidia,low-power-mode", 0); + drive_group[0].lpmd = dev_read_u32_default(config, "nvidia,low-power-mode", PMUX_LPMD_NONE); #endif #ifdef TEGRA_PMX_GRPS_HAVE_SCHMT - drive_group[0].schmt = dev_read_u32_default(config, "nvidia,schmitt", 0); + drive_group[0].schmt = dev_read_u32_default(config, "nvidia,schmitt", PMUX_SCHMT_NONE); #endif #ifdef TEGRA_PMX_GRPS_HAVE_HSM - drive_group[0].hsm = dev_read_u32_default(config, "nvidia,high-speed-mode", 0); + drive_group[0].hsm = dev_read_u32_default(config, "nvidia,high-speed-mode", PMUX_HSM_NONE); #endif for (i = 1; i < drvcnt; i++) @@ -142,31 +142,31 @@ static void tegra_pinctrl_set_pin(struct udevice *config, int pincnt) pinmux_group[0].func = i; - pinmux_group[0].pull = dev_read_u32_default(config, "nvidia,pull", 0); - pinmux_group[0].tristate = dev_read_u32_default(config, "nvidia,tristate", 0); + pinmux_group[0].pull = dev_read_u32_default(config, "nvidia,pull", PMUX_PULL_NORMAL); + pinmux_group[0].tristate = dev_read_u32_default(config, "nvidia,tristate", PMUX_TRI_TRISTATE); #ifdef TEGRA_PMX_PINS_HAVE_E_INPUT - pinmux_group[0].io = dev_read_u32_default(config, "nvidia,enable-input", 0); + pinmux_group[0].io = dev_read_u32_default(config, "nvidia,enable-input", PMUX_PIN_NONE); #endif #ifdef TEGRA_PMX_PINS_HAVE_LOCK - pinmux_group[0].lock = dev_read_u32_default(config, "nvidia,lock", 0); + pinmux_group[0].lock = dev_read_u32_default(config, "nvidia,lock", PMUX_PIN_LOCK_DEFAULT); #endif #ifdef TEGRA_PMX_PINS_HAVE_OD - pinmux_group[0].od = dev_read_u32_default(config, "nvidia,open-drain", 0); + pinmux_group[0].od = dev_read_u32_default(config, "nvidia,open-drain", PMUX_PIN_OD_DEFAULT); #endif #ifdef TEGRA_PMX_PINS_HAVE_IO_RESET - pinmux_group[0].ioreset = dev_read_u32_default(config, "nvidia,io-reset", 0); + pinmux_group[0].ioreset = dev_read_u32_default(config, "nvidia,io-reset", PMUX_PIN_IO_RESET_DEFAULT); #endif #ifdef TEGRA_PMX_PINS_HAVE_RCV_SEL - pinmux_group[0].rcv_sel = dev_read_u32_default(config, "nvidia,rcv-sel", 0); + pinmux_group[0].rcv_sel = dev_read_u32_default(config, "nvidia,rcv-sel", PMUX_PIN_RCV_SEL_DEFAULT); #endif #ifdef TEGRA_PMX_PINS_HAVE_E_IO_HV - pinmux_group[0].e_io_hv = dev_read_u32_default(config, "nvidia,io-hv", 0); + pinmux_group[0].e_io_hv = dev_read_u32_default(config, "nvidia,io-hv", PMUX_PIN_E_IO_HV_DEFAULT); #endif #ifdef TEGRA_PMX_PINS_HAVE_SCHMT - pinmux_group[0].schmt = dev_read_u32_default(config, "nvidia,schmitt", 0); + pinmux_group[0].schmt = dev_read_u32_default(config, "nvidia,schmitt", PMUX_SCHMT_NONE); #endif #ifdef TEGRA_PMX_PINS_HAVE_HSM - pinmux_group[0].hsm = dev_read_u32_default(config, "nvidia,high-speed-mode", 0); + pinmux_group[0].hsm = dev_read_u32_default(config, "nvidia,high-speed-mode", PMUX_HSM_NONE); #endif for (i = 1; i < pincnt; i++) |