diff options
| author | Tom Rini <[email protected]> | 2023-01-10 11:19:45 -0500 |
|---|---|---|
| committer | Tom Rini <[email protected]> | 2023-01-20 12:27:24 -0500 |
| commit | 6e7df1d151a7a127caf3b62ff6dfc003fc2aefcd (patch) | |
| tree | ae38e9dcf468b2e4e58293561fae87895d9b549f /drivers/ram/aspeed | |
| parent | ad242344681f6a0076a6bf100aa83ac9ecbea355 (diff) | |
global: Finish CONFIG -> CFG migration
At this point, the remaining places where we have a symbol that is
defined as CONFIG_... are in fairly odd locations. While as much dead
code has been removed as possible, some of these locations are simply
less obvious at first. In other cases, this code is used, but was
defined in such a way as to have been missed by earlier checks. Perform
a rename of all such remaining symbols to be CFG_... rather than
CONFIG_...
Signed-off-by: Tom Rini <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
Diffstat (limited to 'drivers/ram/aspeed')
| -rw-r--r-- | drivers/ram/aspeed/sdram_ast2600.c | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/drivers/ram/aspeed/sdram_ast2600.c b/drivers/ram/aspeed/sdram_ast2600.c index a2d7ca82fc0..18767554123 100644 --- a/drivers/ram/aspeed/sdram_ast2600.c +++ b/drivers/ram/aspeed/sdram_ast2600.c @@ -104,10 +104,10 @@ * -> WL = AL + CWL + PL = CWL * -> RL = AL + CL + PL = CL */ -#define CONFIG_WL 9 -#define CONFIG_RL 12 -#define T_RDDATA_EN ((CONFIG_RL - 2) << 8) -#define T_PHY_WRLAT (CONFIG_WL - 2) +#define CFG_WL 9 +#define CFG_RL 12 +#define T_RDDATA_EN ((CFG_RL - 2) << 8) +#define T_PHY_WRLAT (CFG_WL - 2) /* MR0 */ #define MR0_CL_12 (BIT(4) | BIT(2)) @@ -974,8 +974,8 @@ static void ast2600_sdrammc_common_init(struct ast2600_sdrammc_regs *regs) /* update CL and WL */ reg = readl(®s->ac_timing[1]); reg &= ~(SDRAM_WL_SETTING | SDRAM_CL_SETTING); - reg |= FIELD_PREP(SDRAM_WL_SETTING, CONFIG_WL - 5) | - FIELD_PREP(SDRAM_CL_SETTING, CONFIG_RL - 5); + reg |= FIELD_PREP(SDRAM_WL_SETTING, CFG_WL - 5) | + FIELD_PREP(SDRAM_CL_SETTING, CFG_RL - 5); writel(reg, ®s->ac_timing[1]); writel(DDR4_MR01_MODE, ®s->mr01_mode_setting); |
